US2014073106A1PendingUtilityA1

Lateral bipolar transistor and cmos hybrid technology

Individually held — no corporate assignee on recordPriority: Sep 12, 2012Filed: Sep 12, 2012Published: Mar 13, 2014
Est. expirySep 12, 2032(~6.1 yrs left)· nominal 20-yr term from priority
H10D 86/01H10D 10/311H10D 10/061H10D 10/041
48
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Claims

Abstract

A method of forming a lateral bipolar transistor. The method includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.

Claims

exact text as granted — not AI-modified
1 - 6 . (canceled) 
     
     
         7 . A method of forming a lateral bipolar transistor comprising the steps of:
 forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of said substrate layer, and a silicon on insulator (SOI) layer on top of said BOX layer;   forming a dummy gate and spacer on top of said silicon on insulator layer;   doping the SOI layer with positive or negative ions;   depositing an inter layer dielectric (ILD);   using chemical mechanical planarization (CMP) to planarize said ILD;   removing said dummy gate creating a cavity that reveals only a base of said dummy gate;   doping said dummy gate base;   growing epitaxially the base contact to the same level as the planarized ILD; and   applying a self-aligned silicide process to form the lateral bipolar transistor.   
     
     
         8 . The method as in  claim 7 , wherein said step of doping said dummy gate base comprises the step of:
 using solid source diffusion on said dummy gate base.   
     
     
         9 . The method as in  claim 7 , wherein said step of doping said dummy gate base comprises the step of:
 implanting said dummy gate base with doping agents.   
     
     
         10 . The method as in  claim 7 , wherein said step of doping said dummy gate base comprises the step of:
 implanting said dummy gate base with doping agents.   
     
     
         11 . The method as in  claim 10 , wherein said step of doping said dummy gate base comprises the step of:
 using solid source diffusion on said dummy gate base.   
     
     
         12 . The method as in  claim 10 , wherein said step of doping said dummy gate base comprises the step of:
 implanting said dummy gate base with doping agents.

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