Inventor · disambiguated record
Houssam Jomaa
Also filed as: JOMAA HOUSSAM · JOMAA HOUSSAM W · JOMAA HOUSSAM WAFIC
33 granted patents·9 pending applications·192 citations·filing 2006–2022
96Inventor score
Top patents by PatentIndex Score
42 records- 0197US9559088B2Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the sameGONZALEZ JAVIER SOTO·Filed 2014·Granted Jan 31, 2017·52 cites·6 claims
- 0296US8736065B2Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the sameGONZALEZ JAVIER SOTO·Filed 2010·Granted May 27, 2014·38 cites·15 claims
- 0394US8421245B2Substrate with embedded stacked through-silicon via dieGONZALEZ JAVIER SOTO·Filed 2010·Granted Apr 16, 2013·19 cites·15 claims
- 0490US9679841B2Substrate and method of forming the sameQUALCOMM INC·Filed 2014·Granted Jun 13, 2017·11 cites·21 claims
- 0589US9536805B2Power management integrated circuit (PMIC) integration into a processor packageQUALCOMM INC·Filed 2014·Granted Jan 3, 2017·12 cites·25 claims
- 0680US10622292B2High density interconnects in an embedded trace substrate (ETS) comprising a core layerQUALCOMM INC·Filed 2018·Granted Apr 14, 2020·3 cites·30 claims
- 0779US8276269B2Dual epoxy dielectric and photosensitive solder mask coatings, and processes of making sameJOMAA HOUSSAM·Filed 2008·Granted Oct 2, 2012·8 cites·21 claims
- 0878US7998857B2Integrated circuit and process for fabricating thereofINTEL CORP·Filed 2007·Granted Aug 16, 2011·6 cites·10 claims
- 0977US10157824B2Integrated circuit (IC) package and package substrate comprising stacked viasQUALCOMM INC·Filed 2017·Granted Dec 18, 2018·3 cites·31 claims
- 1077US9269681B2Surface finish on trace for a thermal compression flip chip (TCFC)QUALCOMM INC·Filed 2013·Granted Feb 23, 2016·4 cites·7 claims
- 1177US8555494B2Method of manufacturing coreless substrateJOMAA HOUSSAM·Filed 2007·Granted Oct 15, 2013·7 cites·20 claims
- 1277US7583871B1Substrates for optical die structuresBCHIR OMAR J·Filed 2008·Granted Sep 1, 2009·8 cites·23 claims
- 1371US7831115B2Optical die structures and associated package substratesINTEL CORP·Filed 2008·Granted Nov 9, 2010·2 cites·23 claims
- 1470US8802556B2Barrier layer on bump and non-wettable coating on traceQUALCOMM INC·Filed 2013·Granted Aug 12, 2014·2 cites·20 claims
- 1567US9398699B2Dual epoxy dielectric and photosensitive solder mask coatings, and processes of making sameJOMAA HOUSSAM·Filed 2012·Granted Jul 19, 2016·1 cites·14 claims
- 1667US9355898B2Package on package (PoP) integrated device comprising a plurality of solder resist layersQUALCOMM INC·Filed 2014·Granted May 31, 2016·2 cites·22 claims
- 1767US9040842B2Mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillersINTEL CORP·Filed 2013·Granted May 26, 2015·1 cites·12 claims
- 1867US7494913B2Microball placement solutionsINTEL CORP·Filed 2006·Granted Feb 24, 2009·5 cites·22 claims
- 1966US7923059B2Method of enabling selective area plating on a substrateINTEL CORP·Filed 2007·Granted Apr 12, 2011·2 cites·8 claims
- 2064US7638877B2Alternative to desmear for build-up roughening and copper adhesion promotionINTEL CORP·Filed 2006·Granted Dec 29, 2009·2 cites·15 claims
- 2163US9609751B2Package substrate comprising surface interconnect and cavity comprising electroless fillQUALCOMM INC·Filed 2014·Granted Mar 28, 2017·1 cites·16 claims
- 2262US8017022B2Selective electroless plating for electronic substratesINTEL CORP·Filed 2007·Granted Sep 13, 2011·1 cites·9 claims
- 2361US11107766B2Substrate with embedded stacked through-silicon via dieINTEL CORP·Filed 2019·Granted Aug 31, 2021·0 cites·14 claims
- 2461US7909977B2Method of manufacturing a substrate for a microelectronic device, and substrate formed therebyINTEL CORP·Filed 2008·Granted Mar 22, 2011·1 cites·11 claims
- 2561US7538021B2Removing dry film resist residues using hydrolyzable membranesINTEL CORP·Filed 2006·Granted May 26, 2009·1 cites·11 claims
- 2653US10461032B2Substrate with embedded stacked through-silicon via dieINTEL CORP·Filed 2013·Granted Oct 29, 2019·0 cites·7 claims
- 2753US8268724B2Alternative to desmear for build-up roughening and copper adhesion promotionJOMAA HOUSSAM·Filed 2009·Granted Sep 18, 2012·0 cites·9 claims
- 2853US2024112999A1Layered glass assembly with pre-patterned electrically conductive interconnectsINTEL CORP·Filed 2022·Application pending·0 cites
- 2952US2014322868A1Barrier layer on bump and non-wettable coating on traceQUALCOMM INC·Filed 2014·Application pending·0 cites
- 3051US9929097B2Mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillersNALLA RAVI·Filed 2015·Granted Mar 27, 2018·0 cites·9 claims
- 3151US2011135883A1Method of manufacturing a substrate for a microelectronic device, and substrate formed therebyJOMAA HOUSSAM·Filed 2011·Application pending·0 cites
- 3250US2011123725A1Method of enabling selective area plating on a substrateBCHIR OMAR J·Filed 2011·Application pending·0 cites
- 3347US8067266B2Methods for the fabrication of microelectronic device substrates by attaching two cores together during fabricationJOMAA HOUSSAM·Filed 2009·Granted Nov 29, 2011·0 cites·18 claims
- 3446US10804195B2High density embedded interconnects in substrateQUALCOMM INC·Filed 2018·Granted Oct 13, 2020·0 cites·24 claims
- 3545US10651160B2Low profile integrated packageQUALCOMM INC·Filed 2018·Granted May 12, 2020·0 cites·29 claims
- 3644US2009152743A1Routing layer for a microelectronic device, microelectronic package containing same, and method of forming a multi-thickness conductor in same for a microelectronic deviceJOMAA HOUSSAM·Filed 2007·Application pending·0 cites
- 3744US2009047783A1Method of removing unwanted plated or conductive material from a substrate, and method of enabling metallization of a substrate using sameBCHIR OMAR J·Filed 2007·Application pending·0 cites
- 3842US2014175658A1Anchoring a trace on a substrate to reduce peeling of the traceQUALCOMM INC·Filed 2013·Application pending·0 cites
- 3942US2014159238A1Package having thermal compression flip chip (tcfc) and chip with reflow bonding on leadQUALCOMM INC·Filed 2012·Application pending·0 cites
- 4040US9941158B2Integrated circuit and process for fabricating thereofGURUMURTHY CHARAN·Filed 2011·Granted Apr 10, 2018·0 cites·10 claims
- 4138US9460980B2Systems, apparatus, and methods for heat dissipationQUALCOMM INC·Filed 2015·Granted Oct 4, 2016·0 cites·30 claims
- 4236US2019067178A1Fine pitch and spacing interconnects with reserve interconnect portionQUALCOMM INC·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →