US2014322868A1PendingUtilityA1

Barrier layer on bump and non-wettable coating on trace

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Assignee: QUALCOMM INCPriority: Nov 14, 2012Filed: Jul 10, 2014Published: Oct 30, 2014
Est. expiryNov 14, 2032(~6.3 yrs left)· nominal 20-yr term from priority
H10W 90/734H10W 90/724H10W 74/15H10W 74/012H10W 72/07236H10W 72/07232H10W 72/07221H10W 72/287H10W 72/252H10W 72/241H10W 72/222H10W 72/073H10W 72/072H10W 72/29H10W 72/019H10W 70/69H10W 70/66H10W 70/687H10W 72/90H01L 24/03H01L 24/06H05K 1/092
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Claims

Abstract

Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.

Claims

exact text as granted — not AI-modified
1 - 20 . (canceled) 
     
     
         21 . A packaging substrate comprising:
 a substrate; and   a trace coupled to the substrate, the trace having a first wettable portion and a second oxidized portion, the first wettable portion being the first portion of the trace that solder can wet onto, the second oxidized portion being coated with an oxide, wherein the oxide is configured to prevent solder from wetting to the second portion of the trace.   
     
     
         22 . The packaging substrate of  claim 21 , wherein the trace is a copper trace. 
     
     
         23 . The packaging substrate of  claim 21 , wherein the second oxidized portion is coated with a nickel oxide. 
     
     
         24 . The packaging substrate of  claim 21 , wherein the second oxidized portion is coated with a chromium oxide. 
     
     
         25 . The packaging substrate of  claim 21 , wherein the packaging substrate is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer. 
     
     
         26 . A packaging substrate comprising:
 a substrate; and   a first interconnect means coupled to the substrate, the first interconnect means having a first wettable portion and a second oxidized portion, the first wettable portion being the first portion of the first interconnect means that solder can wet onto, the second oxidized portion being coated with an oxide, wherein the oxide is configured to prevent solder from wetting to the second portion of the first interconnect means.   
     
     
         27 . The packaging substrate of  claim 26 , wherein the first interconnect means is a copper trace. 
     
     
         28 . The packaging substrate of  claim 26 , wherein the second oxidized portion is coated with a nickel oxide. 
     
     
         29 . The packaging substrate of  claim 26 , wherein the second oxidized portion is coated with a chromium oxide. 
     
     
         30 . The packaging substrate of  claim 26 , wherein the packaging substrate is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer. 
     
     
         31 . A method for manufacturing a packaging substrate, comprising:
 providing a substrate; and   providing a trace coupled to the substrate, the trace having a first wettable portion and a second oxidized portion, the first wettable portion being the first portion of the trace that solder can wet onto, the second oxidized portion being coated with an oxide, wherein the oxide is configured to prevent solder from wetting to the second portion of the trace.   
     
     
         32 . The method of  claim 31 , wherein the trace is a copper trace. 
     
     
         33 . The method of  claim 31 , wherein the second oxidized portion is coated with a nickel oxide. 
     
     
         34 . The method of  claim 31 , wherein the second oxidized portion is coated with a chromium oxide. 
     
     
         35 . A method for assembling a semiconductor package, comprising:
 providing a die that includes an under bump metallization (UBM) structure and a barrier layer, the UBM structure having a first oxide property, the barrier layer coupled to the UBM structure, the barrier layer having a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure, the barrier layer comprising a top portion, a bottom portion and a side portion, the top portion coupled to the UBM structure, the side portion being substantially oxidized;   providing a packaging substrate comprising a trace, the trace having a first wettable portion and a second oxidized portion, the first wettable portion being the first portion of the trace that solder can wet onto, the second oxidized portion being coated with an oxide, wherein the oxide is configured to prevent solder from wetting to the second portion of the trace; and   coupling the die to the packaging substrate to define the semiconductor package.   
     
     
         36 . The method of  claim 35 , wherein the barrier layer having the second oxide property that is more resistant to oxide removal from the flux material than the first oxide of the UBM structure, wherein the barrier layer is configured to prevent the solder from spreading to a side of the UBM structure during an assembly process of the die to a substrate. 
     
     
         37 . The method of  claim 35 , wherein the barrier layer having the second oxide property that is more resistant to oxide removal from the flux material than the first oxide of the UBM structure, wherein the barrier layer is configured to prevent joint starvation between the solder and a trace during an assembly process of the die to a substrate. 
     
     
         38 . A method for providing a trace on a packaging substrate, comprising:
 applying a resist layer on a portion of the trace;   coat an exposed portion of the trace with an oxide, wherein the oxide is configured to prevent solder from wetting to the coated portion of the trace; and   removing the applied resist layer.   
     
     
         39 . The method of  claim 38 , wherein coating the exposed portion of the trace comprises oxidizing the exposed portion. 
     
     
         40 . The method of  claim 38 , wherein coating the exposed portion of the trace comprises plating the exposed portion with a coating material having an oxide property that is more resistant to oxide removal from the flux material than the oxide of the trace. 
     
     
         41 . The method of  claim 40 , wherein the plated material includes an oxide. 
     
     
         42 . The method of  claim 40 , wherein the coating material is a nickel oxide. 
     
     
         43 . The method of  claim 40 , wherein the coating material a chromium oxide.

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