Inventor · disambiguated record
Hsueh-Chung Chen
Also filed as: CHEN HSUEH-CHUNG · CHEN HSUEH-CHUNG H
130 granted patents·48 pending applications·1,120 citations·filing 1997–2024
99Inventor score
Files withIBM86UNITED MICROELECTRONICS CORP27TAIWAN SEMICONDUCTOR MFG21GLOBALFOUNDRIES INC9APPLIED MATERIALS INC8
Top patents by PatentIndex Score
178 records- 0197US11923246B2Via CD controllable top via structureIBM·Filed 2021·Granted Mar 5, 2024·4 cites·10 claims
- 0297US9716038B2Critical dimension shrink through selective metal growth on metal hardmask sidewallsIBM·Filed 2016·Granted Jul 25, 2017·12 cites·1 claims
- 0397US7235424B2Method and apparatus for enhanced CMP planarization using surrounded dummy designTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jun 26, 2007·150 cites·16 claims
- 0495US12010930B2Wrap-around projection liner for AI deviceIBM·Filed 2021·Granted Jun 11, 2024·2 cites·20 claims
- 0595US9576901B1Contact area structure and method for manufacturing the sameIBM·Filed 2016·Granted Feb 21, 2017·12 cites·18 claims
- 0695US9257334B2Double self-aligned via patterningIBM·Filed 2015·Granted Feb 9, 2016·13 cites·7 claims
- 0795US9219007B2Double self aligned via patterningIBM·Filed 2013·Granted Dec 22, 2015·24 cites·14 claims
- 0894US9595473B2Critical dimension shrink through selective metal growth on metal hardmask sidewallsIBM·Filed 2015·Granted Mar 14, 2017·7 cites·15 claims
- 0994US7371663B2Three dimensional IC device and alignment methods of IC device substratesTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted May 13, 2008·22 cites·8 claims
- 1093US12094774B2Back-end-of-line single damascene top via spacer defined by pillar mandrelsIBM·Filed 2021·Granted Sep 17, 2024·2 cites·8 claims
- 1193US7803713B2Method for fabricating air gap for semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Sep 28, 2010·22 cites·20 claims
- 1293US7651893B2Metal electrical fuse structureTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jan 26, 2010·28 cites·13 claims
- 1392US7615841B2Design structure for coupling noise preventionTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Nov 10, 2009·26 cites·12 claims
- 1492US7348672B2Interconnects with improved reliabilityTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Mar 25, 2008·23 cites·19 claims
- 1591US10276434B1Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integrationIBM·Filed 2018·Granted Apr 30, 2019·6 cites·20 claims
- 1691US9953916B2Critical dimension shrink through selective metal growth on metal hardmask sidewallsIBM·Filed 2017·Granted Apr 24, 2018·4 cites·20 claims
- 1790US6544373B2Polishing pad for a chemical mechanical polishing processUNITED MICROELECTRONICS CORP·Filed 2001·Granted Apr 8, 2003·42 cites·12 claims
- 1889US11489111B2Reversible resistive memory logic gate deviceIBM·Filed 2021·Granted Nov 1, 2022·2 cites·20 claims
- 1989US11056426B2Metallization interconnect structure formationIBM·Filed 2019·Granted Jul 6, 2021·6 cites·20 claims
- 2088US10553789B1Fully aligned semiconductor device with a skip-level viaIBM·Filed 2018·Granted Feb 4, 2020·4 cites·20 claims
- 2187US11600325B2Non volatile resistive memory logic deviceIBM·Filed 2020·Granted Mar 7, 2023·2 cites·19 claims
- 2287US6559004B1Method for forming three dimensional semiconductor structure and three dimensional capacitorUNITED MICROELECTRONICS CORP·Filed 2001·Granted May 6, 2003·51 cites·15 claims
- 2387US5872045AMethod for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolationIND TECH RES INST·Filed 1997·Granted Feb 16, 1999·96 cites·21 claims
- 2486US10032633B1Image transfer using EUV lithographic structure and double patterning processIBM·Filed 2017·Granted Jul 24, 2018·3 cites·4 claims
- 2585US11670580B2Subtractive via etch for MIMCAPIBM·Filed 2021·Granted Jun 6, 2023·1 cites·17 claims
- 2685US10168075B2Critical dimension shrink through selective metal growth on metal hardmask sidewallsIBM·Filed 2018·Granted Jan 1, 2019·2 cites·20 claims
- 2785US9385123B2STI region for small fin pitch in FinFET devicesIBM·Filed 2014·Granted Jul 5, 2016·6 cites·8 claims
- 2883US9842805B2Drive-in Mn before copper platingIBM·Filed 2015·Granted Dec 12, 2017·4 cites·20 claims
- 2983US6093089AApparatus for controlling uniformity of polished materialUNITED MICROELECTRONICS CORP·Filed 1999·Granted Jul 25, 2000·55 cites·10 claims
- 3082US11164778B2Barrier-free vertical interconnect structureIBM·Filed 2019·Granted Nov 2, 2021·3 cites·6 claims
- 3182US11152298B2Metal via structureIBM·Filed 2019·Granted Oct 19, 2021·3 cites·18 claims
- 3282US9953915B2Electrically conductive interconnect including via having increased contact surface areaIBM·Filed 2016·Granted Apr 24, 2018·3 cites·18 claims
- 3382US8957519B2Structure and metallization process for advanced technology nodesYANG CHIH-CHAO·Filed 2010·Granted Feb 17, 2015·5 cites·14 claims
- 3482US7781892B2Interconnect structure and method of fabricating sameTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Aug 24, 2010·12 cites·20 claims
- 3581US11133216B2Interconnect structureIBM·Filed 2018·Granted Sep 28, 2021·3 cites·14 claims
- 3681US10818494B2Metal on metal multiple patterningGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 27, 2020·2 cites·20 claims
- 3780US10741751B2Fully aligned semiconductor device with a skip-level viaIBM·Filed 2019·Granted Aug 11, 2020·1 cites·20 claims
- 3880US9330965B2Double self aligned via patterningIBM·Filed 2015·Granted May 3, 2016·2 cites·16 claims
- 3980US9214429B2Trench interconnect having reduced fringe capacitanceST MICROELECTRONICS INC·Filed 2013·Granted Dec 15, 2015·5 cites·20 claims
- 4079US10615027B1Stack viabar structuresIBM·Filed 2018·Granted Apr 7, 2020·2 cites·20 claims
- 4179US7538346B2Semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted May 26, 2009·5 cites·11 claims
- 4278US10937653B2Multiple patterning scheme integration with planarized cut patterningIBM·Filed 2019·Granted Mar 2, 2021·1 cites·19 claims
- 4378US6750129B2Process for forming fusible linksINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jun 15, 2004·27 cites·27 claims
- 4477US6077147AChemical-mechanical polishing station with end-point monitoring deviceUNITED MICROELECTRONICS CORP·Filed 1999·Granted Jun 20, 2000·42 cites·10 claims
- 4576US10825726B2Metal spacer self aligned multi-patterning integrationIBM·Filed 2018·Granted Nov 3, 2020·2 cites·7 claims
- 4676US7714443B2Pad structure design with reduced densityTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted May 11, 2010·7 cites·20 claims
- 4775US9653571B2Freestanding spacer having sub-lithographic lateral dimension and method of forming sameIBM·Filed 2015·Granted May 16, 2017·2 cites·20 claims
- 4875US6344408B1Method for improving non-uniformity of chemical mechanical polishing by over coatingUNITED MICROELECTRONICS CORP·Filed 1999·Granted Feb 5, 2002·44 cites·20 claims
- 4975US6110826ADual damascene process using selective W CVDIND TECH RES INST·Filed 1998·Granted Aug 29, 2000·49 cites·33 claims
- 5074US10784119B2Multiple patterning with lithographically-defined cutsGLOBALFOUNDRIES INC·Filed 2018·Granted Sep 22, 2020·2 cites·20 claims
Showing the top 50 of 178 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →