Inventor · disambiguated record
Joachim Patzer
Also filed as: PATZER JOACHIM
12 granted patents·1 pending application·40 citations·filing 2005–2014
87Inventor score
Top patents by PatentIndex Score
13 records- 0185US8889022B2Methods of forming asymmetric spacers on various structures on integrated circuit productsGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 18, 2014·7 cites·23 claims
- 0284US7183188B2Method for fabricating contact-making connectionsINFINEON TECHNOLOGIES AG·Filed 2005·Granted Feb 27, 2007·16 cites·11 claims
- 0375US8969190B2Methods of forming a layer of silicon on a layer of silicon/germaniumKRONHOLZ STEPHAN·Filed 2012·Granted Mar 3, 2015·3 cites·24 claims
- 0475US8765542B1Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regionsGLOBALFOUNDARIES INC·Filed 2013·Granted Jul 1, 2014·4 cites·16 claims
- 0573US9177874B2Method of forming a semiconductor device employing an optical planarization layerGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 3, 2015·4 cites·22 claims
- 0672US9064961B2Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2013·Granted Jun 23, 2015·3 cites·19 claims
- 0769US8906794B1Gate silicidationGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 9, 2014·2 cites·11 claims
- 0861US9646838B2Method of forming a semiconductor structure including silicided and non-silicided circuit elementsGLOBALFOUNDRIES INC·Filed 2014·Granted May 9, 2017·1 cites·27 claims
- 0954US9034746B2Gate silicidationGLOBALFOUNDRIES INC·Filed 2014·Granted May 19, 2015·0 cites·12 claims
- 1046US9111756B2Integrated circuits with protected resistors and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 18, 2015·0 cites·15 claims
- 1145US9177871B2Balancing asymmetric spacersGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 3, 2015·0 cites·21 claims
- 1243US9029919B2Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layerGLOBALFOUNDRIES INC·Filed 2013·Granted May 12, 2015·0 cites·18 claims
- 1339US2006148227A1Method for fabricating a first contact hole plane in a memory moduleINFINEON TECHNOLOGIES AG·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →