Inventor · disambiguated record
Kyuwon Lee
Also filed as: LEE KYUWON
18 granted patents·4 pending applications·191 citations·filing 2008–2023
94Inventor score
Top patents by PatentIndex Score
22 records- 0196US8502387B2Integrated circuit packaging system with vertical interconnection and method of manufacture thereofCHOI DAESIK·Filed 2010·Granted Aug 6, 2013·48 cites·20 claims
- 0293US8004093B2Integrated circuit package stacking systemSTATS CHIPPAC LTD·Filed 2008·Granted Aug 23, 2011·37 cites·18 claims
- 0392US7683469B2Package-on-package system with heat spreaderSTATS CHIPPAC LTD·Filed 2008·Granted Mar 23, 2010·32 cites·20 claims
- 0491US8273604B2Semiconductor device and method of forming WLCSP structure using protruded MLPKIM OHHAN·Filed 2011·Granted Sep 25, 2012·17 cites·22 claims
- 0590US8519544B2Semiconductor device and method of forming WLCSP structure using protruded MLPKIM OHHAN·Filed 2012·Granted Aug 27, 2013·13 cites·25 claims
- 0687US9401347B2Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSVSTATS CHIPPAC LTD·Filed 2015·Granted Jul 26, 2016·5 cites·24 claims
- 0786US8531012B2Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSVLEE SINJAE·Filed 2009·Granted Sep 10, 2013·13 cites·22 claims
- 0885US8574964B2Semiconductor device and method of forming electrical interconnection between semiconductor die and substrate with continuous body of solder tapeCHO SUNGWON·Filed 2010·Granted Nov 5, 2013·7 cites·25 claims
- 0981US8932908B2Semiconductor device and method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor dieSTATS CHIPPAC LTD·Filed 2013·Granted Jan 13, 2015·5 cites·30 claims
- 1079US8432028B2Integrated circuit packaging system with package-on-package and method of manufacture thereofKIM JINGWAN·Filed 2011·Granted Apr 30, 2013·8 cites·20 claims
- 1173US12211778B2Semiconductor device and method of forming bump pad array on substrate for ground connection for heat sink/shielding structureSTATS CHIPPAC PTE LTD·Filed 2023·Granted Jan 28, 2025·0 cites·31 claims
- 1272US8937371B2Semiconductor device and method of forming a shielding layer over a semiconductor die disposed in a cavity of an interconnect structure and grounded through the die TSVSTATS CHIPPAC LTD·Filed 2013·Granted Jan 20, 2015·2 cites·24 claims
- 1366US11764136B2Semiconductor device and method of forming bump pad array on substrate for ground connection for heat sink/shielding structureSTATS CHIPPAC PTE LTD·Filed 2021·Granted Sep 19, 2023·0 cites·31 claims
- 1464US8310038B2Integrated circuit packaging system with embedded conductive structure and method of manufacture thereofKIM JINGWAN·Filed 2011·Granted Nov 13, 2012·2 cites·20 claims
- 1564US8288202B2Method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor dieLEE KYUWON·Filed 2010·Granted Oct 16, 2012·2 cites·20 claims
- 1658US2023288799A1Method of forming patternsSAMSUNG SDI CO LTD·Filed 2022·Application pending·0 cites
- 1753US9082887B1Integrated circuit packaging system with posts and method of manufacture thereofCHOI DAESIK·Filed 2013·Granted Jul 14, 2015·0 cites·20 claims
- 1851US2023230893A1Semiconductor Device and Method of Stabilizing Heat Spreader on Semiconductor PackageSTATS CHIPPAC PTE LTD·Filed 2022·Application pending·0 cites
- 1950US2014008783A1Semiconductor Device and Method of Forming Electrical Interconnection Between Semiconductor Die and Substrate with Continuous Body of Solder TapeSTATS CHIPPAC LTD·Filed 2013·Application pending·0 cites
- 2047US8502392B2Semiconductor device with partially-etched conductive layer recessed within substrate for bonding to semiconductor dieLEE KYUWON·Filed 2012·Granted Aug 6, 2013·0 cites·25 claims
- 2144US2011291264A1Integrated circuit packaging system with posts and method of manufacture thereofCHOI DAESIK·Filed 2010·Application pending·0 cites
- 2240US11775729B2Technology file process rule validationSAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted Oct 3, 2023·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →