Inventor · disambiguated record
Liu Jiang
Also filed as: JIANG LIU · JIANG LIU-QUAN
11 granted patents·6 pending applications·35 citations·filing 2014–2024
84Inventor score
Files withAPPLIED MATERIALS INC7GLOBALFOUNDRIES INC5GLOBALFOUNDRIES US INC4SHENZHEN YUXINXIN ELECTRONICS CO LTD1
Top patents by PatentIndex Score
17 records- 0181US10756184B2Faceted epitaxial source/drain regionsGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 25, 2020·3 cites·17 claims
- 0279US10957578B2Single diffusion break device for FDSOIGLOBALFOUNDRIES US INC·Filed 2018·Granted Mar 23, 2021·2 cites·20 claims
- 0377US10825897B2Formation of enhanced faceted raised source/drain EPI material for transistor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 3, 2020·2 cites·14 claims
- 0477US10777642B2Formation of enhanced faceted raised source/drain epi material for transistor devicesGLOBALFOUNDRIES INC·Filed 2019·Granted Sep 15, 2020·2 cites·18 claims
- 0576US11018221B2Air gap regions of a semiconductor deviceGLOBALFOUNDRIES US INC·Filed 2019·Granted May 25, 2021·2 cites·12 claims
- 0674USD758990SHeadphonesSHENZHEN YUXINXIN ELECTRONICS CO LTD·Filed 2014·Granted Jun 14, 2016·24 cites·1 claims
- 0766US2024234544A1Inner spacer liner for gate-all-around deviceAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 0866US2025121472A1Polishing articles for hybrid bonding applicationsAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 0961US2024407170A1Structure and fabrication method of peripheral transistor with epi-si contacts in memory devicesAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 1059US2025259958A1Bonding Layers Formed of High Thermal Conductivity MaterialsAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 1158US2024234531A1Inner spacer liner for gate-all-around deviceAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 1257US2024194757A1Multilayer inner spacer for gate-all-around deviceAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 1354US11899376B1Methods for forming alignment marksAPPLIED MATERIALS INC·Filed 2022·Granted Feb 13, 2024·0 cites·20 claims
- 1450US10797049B2FinFET structure with dielectric bar containing gate to reduce effective capacitance, and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 6, 2020·0 cites·17 claims
- 1549US11171036B2Preventing dielectric void over trench isolation regionGLOBALFOUNDRIES US INC·Filed 2019·Granted Nov 9, 2021·0 cites·15 claims
- 1649US10546775B1Field-effect transistors with improved dielectric gap fillGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 28, 2020·0 cites·19 claims
- 1748US11164794B2Semiconductor structures in a wide gate pitch region of semiconductor devicesGLOBALFOUNDRIES US INC·Filed 2019·Granted Nov 2, 2021·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →