Inventor · disambiguated record
Soo Han Choi
Also filed as: CHOI SOO H · CHOI SOO HAN
17 granted patents·1 pending application·175 citations·filing 1995–2022
93Inventor score
Top patents by PatentIndex Score
18 records- 0197US8954913B1Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rulesGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 10, 2015·43 cites·12 claims
- 0295US9747407B2Categorized stitching guidance for triple-patterning technologySYNOPSYS INC·Filed 2015·Granted Aug 29, 2017·12 cites·18 claims
- 0395US8969199B1Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning processGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 3, 2015·25 cites·19 claims
- 0488US9141751B2Method of forming a patternSAMSUNG ELECTRONICS CO LTD·Filed 2013·Granted Sep 22, 2015·9 cites·20 claims
- 0581US10261412B2Categorized stitching guidance for triple-patterning technologySYNOPSYS INC·Filed 2017·Granted Apr 16, 2019·2 cites·29 claims
- 0680US9613177B2Methods of generating circuit layouts that are to be manufactured using SADP routing techniquesGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 4, 2017·4 cites·16 claims
- 0778US5827571AHot-wall CVD method for forming a ferroelectric filmHYUNDAI ELECTRONICS IND·Filed 1997·Granted Oct 27, 1998·58 cites·11 claims
- 0870US9158879B2Color-insensitive rules for routing structuresGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 13, 2015·2 cites·12 claims
- 0963US8045787B2System for analyzing mask topography and method of forming image using the systemSAMSUNG ELECTRONICS CO LTD·Filed 2008·Granted Oct 25, 2011·2 cites·14 claims
- 1051US9400863B2Color-insensitive rules for routing structuresGLOBALFOUNDRIES INC·Filed 2015·Granted Jul 26, 2016·0 cites·14 claims
- 1149US7361435B2Method of creating a layout of a set of masksSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Apr 22, 2008·0 cites·12 claims
- 1247US12032894B2System and method for synchronizing net text across hierarchical levelsSYNOPSYS INC·Filed 2021·Granted Jul 9, 2024·0 cites·14 claims
- 1347US11972191B2System and method for providing enhanced net pruningSYNOPSYS INC·Filed 2021·Granted Apr 30, 2024·0 cites·19 claims
- 1447US5614429AMethod for fabricating EEPROM with control gate in touch with select gateHYUNDAI ELECTRONICS IND·Filed 1995·Granted Mar 25, 1997·10 cites·3 claims
- 1545US2022350950A1Layout versus schematic (lvs) device extraction using pattern matchingSYNOPSYS INC·Filed 2022·Application pending·0 cites
- 1644US7097949B2Phase edge phase shift mask enforcing a width of a field gate image and fabrication method thereofSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Aug 29, 2006·1 cites·11 claims
- 1743US5710735AEEPROM and method for fabricating the sameHYUNDAI ELECTRONICS IND·Filed 1996·Granted Jan 20, 1998·7 cites·4 claims
- 1842US6998199B2Mask for manufacturing a highly-integrated circuit deviceSAMSUNG ELECTRONICS CO LTD·Filed 2002·Granted Feb 14, 2006·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →