Inventor · disambiguated record
Somchai Nondhasitthichai
Also filed as: NONDHASITTHICHAI SOMCHAI
35 granted patents·1 pending application·458 citations·filing 2003–2017
97Inventor score
Files withUTAC THAI LTD11NONDHASITTHICHAI SOMCHAI9SIRINORAKUL SARAVUTH9UTAC HEADQUARTERS PTE LTD4NS ELECTRONICS BANGKOK 1993 LT3
Top patents by PatentIndex Score
36 records- 0196US8063470B1Method and apparatus for no lead semiconductor packageSIRINORAKUL SARAVUTH·Filed 2008·Granted Nov 22, 2011·41 cites·16 claims
- 0295US7060535B1Flat no-lead semiconductor die package including stud terminalsNS ELECTRONICS BANGKOK 1993 LT·Filed 2003·Granted Jun 13, 2006·179 cites·37 claims
- 0394US7327017B2Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compoundUTAC THAI LTD·Filed 2005·Granted Feb 5, 2008·40 cites·22 claims
- 0493US8129229B1Method of manufacturing semiconductor package containing flip-chip arrangementSIRINORAKUL SARAVUTH·Filed 2010·Granted Mar 6, 2012·18 cites·14 claims
- 0591US7205180B1Process of fabricating semiconductor packages using leadframes roughened with chemical etchantNS ELECTRONICS BANGKOK 1993 LT·Filed 2004·Granted Apr 17, 2007·60 cites·76 claims
- 0690US9741642B1Semiconductor package with partial plating on contact side surfacesUTAC HEADQUARTERS PTE LTD·Filed 2016·Granted Aug 22, 2017·8 cites·21 claims
- 0788US7790512B1Molded leadframe substrate semiconductor packageUTAC THAI LTD·Filed 2008·Granted Sep 7, 2010·14 cites·21 claims
- 0887US8338922B1Molded leadframe substrate semiconductor packageSIRINORAKUL SARAVUTH·Filed 2010·Granted Dec 25, 2012·8 cites·9 claims
- 0982US10515878B1Semiconductor package with partial plating on contact side surfacesUTAC HEADQUARTERS PTE LTD·Filed 2017·Granted Dec 24, 2019·3 cites·16 claims
- 1082US9773722B1Semiconductor package with partial plating on contact side surfacesUTAC HEADQUARTERS PTE LTD·Filed 2015·Granted Sep 26, 2017·4 cites·20 claims
- 1180US9082607B1Molded leadframe substrate semiconductor packageNONDHASITTHICHAI SOMCHAI·Filed 2007·Granted Jul 14, 2015·4 cites·16 claims
- 1280US8013437B1Package with heat transferUTAC THAI LTD·Filed 2007·Granted Sep 6, 2011·9 cites·20 claims
- 1380US7153724B1Method of fabricating no-lead package for semiconductor die with half-etched leadframeNS ELECTRONICS BANGKOK 1993 LT·Filed 2003·Granted Dec 26, 2006·36 cites·10 claims
- 1475US9099317B2Method for forming lead frame land grid arrayNONDHASITTHICHAI SOMCHAI·Filed 2009·Granted Aug 4, 2015·4 cites·25 claims
- 1575US8575762B2Very extremely thin semiconductor packageNONDHASITTHICHAI SOMCHAI·Filed 2007·Granted Nov 5, 2013·4 cites·20 claims
- 1674US9349679B2Singulation method for semiconductor package with plating on side of connectorsSIRINORAKUL SARAVUTH·Filed 2011·Granted May 24, 2016·3 cites·19 claims
- 1774US8071426B2Method and apparatus for no lead semiconductor packageSIRINORAKUL SARAVUTH·Filed 2010·Granted Dec 6, 2011·3 cites·20 claims
- 1871US8125077B2Package with heat transferSIRINORAKUL SARAVUTH·Filed 2010·Granted Feb 28, 2012·3 cites·21 claims
- 1969US9761435B1Flip chip cavity packageSIRINORAKUL SARAVUTH·Filed 2008·Granted Sep 12, 2017·4 cites·16 claims
- 2067US9711343B1Molded leadframe substrate semiconductor packageNONDHASITTHICHAI SOMCHAI·Filed 2007·Granted Jul 18, 2017·1 cites·21 claims
- 2167US8704381B2Very extremely thin semiconductor packageUTAC THAI LTD·Filed 2013·Granted Apr 22, 2014·1 cites·12 claims
- 2266US8487451B2Lead frame land grid array with routing connector trace under unitNONDHASITTHICHAI SOMCHAI·Filed 2011·Granted Jul 16, 2013·2 cites·24 claims
- 2366US7922877B2Method and apparatus for plating a semiconductor packageUTAC THAI LTD·Filed 2009·Granted Apr 12, 2011·0 cites·8 claims
- 2465US8492906B2Lead frame ball grid array with traces under dieNONDHASITTHICHAI SOMCHAI·Filed 2011·Granted Jul 23, 2013·2 cites·13 claims
- 2565US7572168B1Method and apparatus for high speed singulationUTAC THAI LTD·Filed 2007·Granted Aug 11, 2009·6 cites·37 claims
- 2661US7718522B2Method and apparatus for plating a semiconductor packageUTAC THAI LTD·Filed 2008·Granted May 18, 2010·0 cites·11 claims
- 2760US8652879B2Lead frame ball grid array with traces under dieUTAC THAI LTD·Filed 2013·Granted Feb 18, 2014·1 cites·18 claims
- 2858US9093486B2Molded leadframe substrate semiconductor packageUTAC THAI LTD·Filed 2013·Granted Jul 28, 2015·0 cites·5 claims
- 2956US9099294B1Molded leadframe substrate semiconductor packageNONDHASITTHICHAI SOMCHAI·Filed 2009·Granted Aug 4, 2015·0 cites·18 claims
- 3055US9196470B1Molded leadframe substrate semiconductor packageNONDHASITTHICHAI SOMCHAI·Filed 2009·Granted Nov 24, 2015·0 cites·17 claims
- 3153US9899208B2Molded leadframe substrate semiconductor packageNONDHASITTHICHAI SOMCHAI·Filed 2010·Granted Feb 20, 2018·0 cites·5 claims
- 3252US9818676B2Singulation method for semiconductor package with plating on side of connectorsUTAC THAI LTD·Filed 2016·Granted Nov 14, 2017·0 cites·20 claims
- 3350US8685794B2Lead frame land grid array with routing connector trace under unitUTAC THAI LTD·Filed 2013·Granted Apr 1, 2014·0 cites·20 claims
- 3449US10204850B1Semiconductor package with partial plating on contact side surfacesUTAC HEADQUARTERS PTE LTD·Filed 2017·Granted Feb 12, 2019·0 cites·17 claims
- 3540US2012066899A1Qfn process for strip testSIRINORAKUL SARAVUTH·Filed 2011·Application pending·0 cites
- 3639US9947605B2Flip chip cavity packageSIRINORAKUL SARAVUTH·Filed 2010·Granted Apr 17, 2018·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →