Inventor · disambiguated record
Tek Po Rinus Lee
Also filed as: LEE TEK PO R · LEE TEK PO RINUS
14 granted patents·6 pending applications·104 citations·filing 2004–2024
90Inventor score
Top patents by PatentIndex Score
20 records- 0198US10103238B1Nanosheet field-effect transistor with full dielectric isolationGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 16, 2018·57 cites·20 claims
- 0296US9831317B1Buried contact structures for a vertical field-effect transistorGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 28, 2017·18 cites·10 claims
- 0395US10263122B1Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistorGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 16, 2019·14 cites·10 claims
- 0489US9876077B1Methods of forming a protection layer on an isolation region of IC products comprising FinFET devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 23, 2018·5 cites·17 claims
- 0581US10872979B2Spacer structures for a transistor deviceGLOBALFOUNDRIES INC·Filed 2020·Granted Dec 22, 2020·1 cites·17 claims
- 0680US10242982B2Method for forming a protection device having an inner contact spacer and the resulting devicesGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 26, 2019·3 cites·18 claims
- 0779US9570552B1Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistorsGLOBALFOUNDRIES INC·Filed 2016·Granted Feb 14, 2017·3 cites·20 claims
- 0873US10170544B2Integrated circuit products that include FinFET devices and a protection layer formed on an isolation regionGLOBALFOUNDRIES INC·Filed 2017·Granted Jan 1, 2019·1 cites·20 claims
- 0972US10629739B2Methods of forming spacers adjacent gate structures of a transistor deviceGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 21, 2020·1 cites·19 claims
- 1067US10230000B2Vertical-transport transistors with self-aligned contactsGLOBALFOUNDRIES INC·Filed 2017·Granted Mar 12, 2019·1 cites·19 claims
- 1162US2025164891A1Layer stack for extreme ultraviolet lithographyTOKYO ELECTRON LTD·Filed 2023·Application pending·0 cites
- 1258US2025105002A1Method for semiconductor processingTOKYO ELECTRON LTD·Filed 2023·Application pending·0 cites
- 1357US10276683B2Common metal contact regions having different Schottky barrier heights and methods of manufacturing sameGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 30, 2019·0 cites·15 claims
- 1456US2025349606A1Mixed-species buffer film for structural integrity of metallizationTOKYO ELECTRON LTD·Filed 2024·Application pending·0 cites
- 1553US9812543B2Common metal contact regions having different Schottky barrier heights and methods of manufacturing sameGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 7, 2017·0 cites·6 claims
- 1653US2025157932A1Low resistance linerTOKYO ELECTRON LTD·Filed 2023·Application pending·0 cites
- 1750US10109714B2Buried contact structures for a vertical field-effect transistorGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 23, 2018·0 cites·13 claims
- 1848US10886178B2Device with highly active acceptor doping and method of production thereofGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 5, 2021·0 cites·20 claims
- 1936US2018138177A1Formation of band-edge contactsGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 2030US2007272955A1Reliable ContactsAGENCY SCIENCE TECH & RES·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →