Inventor · disambiguated record
Teck Jung Tang
Also filed as: TANG TECK J · TANG TECK JUNG
11 granted patents·4 pending applications·38 citations·filing 2006–2024
87Inventor score
Files withGLOBALFOUNDRIES INC5CHARTERED SEMICONDUCTOR MFG2GLOBALFOUNDRIES SG PTE LTD2TAN SOON YOENG2CHAN VICTOR W C1
Top patents by PatentIndex Score
15 records- 0192US9576894B2Integrated circuits including organic interlayer dielectric layers and methods for fabricating the sameGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 21, 2017·9 cites·20 claims
- 0284US9142451B2Reduced capacitance interlayer structures and fabrication methodsGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 22, 2015·6 cites·12 claims
- 0382US8969932B2Methods of forming a finfet semiconductor device with undoped finsGLOBALFOUNDRIES INC·Filed 2012·Granted Mar 3, 2015·6 cites·26 claims
- 0480US9105507B2Methods of forming a FinFET semiconductor device with undoped finsGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 11, 2015·3 cites·20 claims
- 0578US8637993B23D integrated circuit system with connecting via structure and method for forming the sameWONG CHUN YU·Filed 2012·Granted Jan 28, 2014·7 cites·19 claims
- 0676US9362162B2Methods of fabricating BEOL interlayer structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 7, 2016·3 cites·20 claims
- 0768US8283193B2Integrated circuit system with sealring and method of manufacture thereofTAN SOON YOENG·Filed 2009·Granted Oct 9, 2012·4 cites·20 claims
- 0851US2025306274A1Structures including a photonic device and an undercutGLOBALFOUNDRIES US INC·Filed 2024·Application pending·0 cites
- 0945US9947645B2Multi-project wafer with IP protection by reticle mask pattern modificationGLOBALFOUNDRIES SG PTE LTD·Filed 2015·Granted Apr 17, 2018·0 cites·20 claims
- 1045US7749894B2Integrated circuit processing systemCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Jul 6, 2010·0 cites·8 claims
- 1144US9069923B2IP protectionTAN SOON YOENG·Filed 2011·Granted Jun 30, 2015·0 cites·19 claims
- 1244US7906426B2Method of controlled low-k via etch for Cu interconnectionsGLOBALFOUNDRIES SG PTE LTD·Filed 2007·Granted Mar 15, 2011·0 cites·17 claims
- 1344US2015348907A1Reduced capacitance interlayer structures and fabrication methodsGLOBAL FOUNDRIES INC·Filed 2015·Application pending·0 cites
- 1440US2009014807A1Dual stress liners for integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 1535US2008246056A1SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFETCHAN VICTOR W C·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →