Inventor · disambiguated record
Victor Moroz
Also filed as: MOROZ VICTOR
149 granted patents·20 pending applications·2,670 citations·filing 2004–2024
99Inventor score
Top patents by PatentIndex Score
169 records- 0199US7960232B2Methods of designing an integrated circuit on corrugated substrateSYNOPSYS INC·Filed 2009·Granted Jun 14, 2011·139 cites·23 claims
- 0299US7528465B2Integrated circuit on corrugated substrateSYNOPSYS INC·Filed 2007·Granted May 5, 2009·347 cites·4 claims
- 0399US7265008B2Method of IC production using corrugated substrateSYNOPSYS INC·Filed 2005·Granted Sep 4, 2007·349 cites·18 claims
- 0499US7247887B2Segmented channel MOS transistorSYNOPSYS INC·Filed 2005·Granted Jul 24, 2007·476 cites·30 claims
- 0599US7190050B2Integrated circuit on corrugated substrateSYNOPSYS INC·Filed 2005·Granted Mar 13, 2007·423 cites·14 claims
- 0698US9953990B1One-time programmable memory using rupturing of gate insulationSYNOPSYS INC·Filed 2017·Granted Apr 24, 2018·21 cites·18 claims
- 0797US8924908B2FinFET cell architecture with power tracesSYNOPSYS INC·Filed 2013·Granted Dec 30, 2014·23 cites·22 claims
- 0897US8723268B2N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitchMOROZ VICTOR·Filed 2012·Granted May 13, 2014·26 cites·33 claims
- 0997US8595661B2N-channel and p-channel finFET cell architectureKAWA JAMIL·Filed 2011·Granted Nov 26, 2013·36 cites·29 claims
- 1097US8561003B2N-channel and P-channel finFET cell architecture with inter-block insulatorKAWA JAMIL·Filed 2011·Granted Oct 15, 2013·43 cites·37 claims
- 1197US7926018B2Method and apparatus for generating a layout for a transistorSYNOPSYS INC·Filed 2007·Granted Apr 12, 2011·108 cites·19 claims
- 1296US7484198B2Managing integrated circuit stress using dummy diffusion regionsSYNOPSYS INC·Filed 2006·Granted Jan 27, 2009·48 cites·8 claims
- 1395US11984384B2Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery networkSYNOPSYS INC·Filed 2021·Granted May 14, 2024·2 cites·13 claims
- 1495US10312229B2Memory cells including vertical nanowire transistorsSYNOPSYS INC·Filed 2017·Granted Jun 4, 2019·16 cites·36 claims
- 1595US9727675B2Parameter extraction of DFTSYNOPSYS INC·Filed 2016·Granted Aug 8, 2017·14 cites·24 claims
- 1695US9547740B2Methods for fabricating high-density integrated circuit devicesSYNOPSYS INC·Filed 2014·Granted Jan 17, 2017·17 cites·15 claims
- 1795US9048121B2FinFET cell architecture with insulator structureSYNOPSYS INC·Filed 2013·Granted Jun 2, 2015·16 cites·13 claims
- 1895US7542891B2Method of correlating silicon stress to device instance parameters for circuit simulationSYNOPSYS INC·Filed 2006·Granted Jun 2, 2009·40 cites·25 claims
- 1994US9400862B2Cells having transistors and interconnects including nanowires or 2D material stripsSYNOPSYS INC·Filed 2014·Granted Jul 26, 2016·21 cites·21 claims
- 2094US8964453B2SRAM layoutsSYNOPSYS INC·Filed 2013·Granted Feb 24, 2015·16 cites·36 claims
- 2194US7413957B2Methods for forming a transistorAPPLIED MATERIALS INC·Filed 2005·Granted Aug 19, 2008·25 cites·18 claims
- 2293US11742247B2Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET)SYNOPSYS INC·Filed 2021·Granted Aug 29, 2023·2 cites·20 claims
- 2393US9691768B2Nanowire or 2D material strips interconnects in an integrated circuit cellSYNOPSYS INC·Filed 2016·Granted Jun 27, 2017·8 cites·24 claims
- 2493US9691764B2FinFET cell architecture with power tracesSYNOPSYS INC·Filed 2015·Granted Jun 27, 2017·7 cites·18 claims
- 2593US8609550B2Methods for manufacturing integrated circuit devices having features with reduced edge curvatureMOROZ VICTOR·Filed 2012·Granted Dec 17, 2013·11 cites·22 claims
- 2693US7939862B2Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layersSYNOPSYS INC·Filed 2007·Granted May 10, 2011·30 cites·5 claims
- 2793US7681164B2Method and apparatus for placing an integrated circuit device within an integrated circuit layoutSYNOPSYS INC·Filed 2007·Granted Mar 16, 2010·31 cites·17 claims
- 2892US9257429B2N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitchSYNOPSYS INC·Filed 2015·Granted Feb 9, 2016·7 cites·36 claims
- 2992US9076673B2FinFET cell architecture with power tracesSYNOPSYS INC·Filed 2014·Granted Jul 7, 2015·8 cites·23 claims
- 3092US8987828B2N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitchSYNOPSYS INC·Filed 2014·Granted Mar 24, 2015·10 cites·11 claims
- 3192US8901615B2N-channel and P-channel end-to-end finfet cell architectureMOROZ VICTOR·Filed 2012·Granted Dec 2, 2014·16 cites·13 claims
- 3291US9378320B2Array with intercell conductors including nanowires or 2D material stripsSYNOPSYS INC·Filed 2014·Granted Jun 28, 2016·9 cites·25 claims
- 3391US7897479B2Managing integrated circuit stress using dummy diffusion regionsSYNOPSYS INC·Filed 2008·Granted Mar 1, 2011·18 cites·14 claims
- 3491US7767515B2Managing integrated circuit stress using stress adjustment trenchesSYNOPSYS INC·Filed 2006·Granted Aug 3, 2010·18 cites·19 claims
- 3591US7600207B2Stress-managed revision of integrated circuit layoutsSYNOPSYS INC·Filed 2006·Granted Oct 6, 2009·24 cites·33 claims
- 3690US11894049B1CFET SRAM cell utilizing 8 transistorsSYNOPSYS INC·Filed 2021·Granted Feb 6, 2024·3 cites·9 claims
- 3790US11342492B1Josephson junction structuresSYNOPSYS INC·Filed 2020·Granted May 24, 2022·2 cites·20 claims
- 3890US9379183B2Methods for manufacturing integrated circuit devices having features with reduced edge curvatureSYNOPSYS INC·Filed 2015·Granted Jun 28, 2016·5 cites·6 claims
- 3990US9361418B2Nanowire or 2D material strips interconnects in an integrated circuit cellSYNOPSYS INC·Filed 2014·Granted Jun 7, 2016·9 cites·26 claims
- 4090US8362622B2Method and apparatus for placing transistors in proximity to through-silicon viasSYNOPSYS INC·Filed 2009·Granted Jan 29, 2013·16 cites·16 claims
- 4189US10049173B2Parameter extraction of DFTSYNOPSYS INC·Filed 2017·Granted Aug 14, 2018·4 cites·20 claims
- 4289US9728528B2Method and apparatus for floating or applying voltage to a well of an integrated circuitSYNOPSYS INC·Filed 2014·Granted Aug 8, 2017·5 cites·22 claims
- 4389US9152750B2Methods for manufacturing integrated circuit devices having features with reduced edge curvatureSYNOPSYS INC·Filed 2014·Granted Oct 6, 2015·6 cites·12 claims
- 4488US11068631B2First principles design automation toolSYNOPSYS INC·Filed 2019·Granted Jul 20, 2021·4 cites·18 claims
- 4588US8786057B2Integrated circuit on corrugated substrateKING TSU-JAE·Filed 2008·Granted Jul 22, 2014·9 cites·1 claims
- 4688US8407634B1Analysis of stress impact on transistor performanceMOROZ VICTOR·Filed 2005·Granted Mar 26, 2013·10 cites·26 claims
- 4787US12041858B1Josephson junction structuresSYNOPSYS INC·Filed 2020·Granted Jul 16, 2024·2 cites·20 claims
- 4887US10831957B2Simulation scaling with DFT and non-DFTSYNOPSYS INC·Filed 2018·Granted Nov 10, 2020·3 cites·12 claims
- 4987US10311200B2Pre-silicon design rule evaluationSYNOPSYS INC·Filed 2016·Granted Jun 4, 2019·7 cites·36 claims
- 5087US10037397B2Memory cell including vertical transistors and horizontal nanowire bit linesSYNOPSYS INC·Filed 2014·Granted Jul 31, 2018·8 cites·10 claims
Showing the top 50 of 169 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →