Inventor · disambiguated record
Xuesong Rao
Also filed as: RAO XUESONG
14 granted patents·4 pending applications·10 citations·filing 2008–2023
86Inventor score
Files withGLOBALFOUNDRIES SG PTE LTD13RAO XUESONG2CHARTERED SEMICONDUCTOR MFG1LEONG LUP SAN1LIU HUANG1
Top patents by PatentIndex Score
18 records- 0186US11545486B2Integrated thin film resistor and metal-insulator-metal capacitorGLOBALFOUNDRIES SG PTE LTD·Filed 2020·Granted Jan 3, 2023·2 cites·16 claims
- 0270US11244915B2Bond pads of semiconductor devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2019·Granted Feb 8, 2022·1 cites·18 claims
- 0369US8940637B2Method for forming through silicon via with wafer backside protectionLEONG LUP SAN·Filed 2012·Granted Jan 27, 2015·3 cites·11 claims
- 0467US9242338B2CMP head structureGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Jan 26, 2016·1 cites·20 claims
- 0562US9511470B2CMP head structure with retaining ringGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Dec 6, 2016·0 cites·20 claims
- 0660US9349654B2Isolation for embedded devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted May 24, 2016·1 cites·21 claims
- 0758US9859236B2Integrated circuits having copper bonding structures with silicon carbon nitride passivation layers thereon and methods for fabricating sameGLOBALFOUNDRIES SG PTE LTD·Filed 2015·Granted Jan 2, 2018·1 cites·20 claims
- 0856US9230886B2Method for forming through silicon via with wafer backside protectionGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Jan 5, 2016·0 cites·17 claims
- 0954US11315876B2Thin film conductive material with conductive etch stop layerGLOBALFOUNDRIES SG PTE LTD·Filed 2020·Granted Apr 26, 2022·0 cites·19 claims
- 1054US9293388B2Reliable passivation layers for semiconductor devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted Mar 22, 2016·1 cites·20 claims
- 1151US11610837B2Via structures of passive semiconductor devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2020·Granted Mar 21, 2023·0 cites·20 claims
- 1251US2024413162A1Cavity with bottom having dielectric layer portion over gate body without etch stop layer and related methodGLOBALFOUNDRIES SG PTE LTD·Filed 2023·Application pending·0 cites
- 1350US9627219B2CMP wafer edge control of dielectricGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Granted Apr 18, 2017·0 cites·21 claims
- 1440US8492236B1Step-like spacer profileRAO XUESONG·Filed 2012·Granted Jul 23, 2013·0 cites·20 claims
- 1538US2009325359A1Integrated circuit system employing a modified isolation structureCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 1637US2014117545A1Copper hillock prevention with hydrogen plasma treatment in a dedicated chamberLIU HUANG·Filed 2012·Application pending·0 cites
- 1737US2016181197A1Reliable passivation layers for semiconductor devicesGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Application pending·0 cites
- 1836US8828858B2Spacer profile engineering using films with continuously increased etch rate from inner to outer surfaceRAO XUESONG·Filed 2012·Granted Sep 9, 2014·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →