Inventor · disambiguated record
Yisuo Li
Also filed as: LI YISUO
22 granted patents·5 pending applications·77 citations·filing 2004–2024
94Inventor score
Files withUNISANTIS ELECT SINGAPORE PTE9CHARTERED SEMICONDUCTOR MFG8CHU SANFORD3GLOBALFOUNDRIES SG PTE LTD2MASUOKA FUJIO2
Top patents by PatentIndex Score
27 records- 0193US12096608B2Pillar-shaped semiconductor device and manufacturing method thereofUNISANTIS ELECT SINGAPORE PTE·Filed 2021·Granted Sep 17, 2024·2 cites·10 claims
- 0293US11862464B2Method for manufacturing three-dimensional semiconductor deviceUNISANTIS ELECT SINGAPORE PTE·Filed 2021·Granted Jan 2, 2024·2 cites·14 claims
- 0389US9153697B2Surrounding gate transistor (SGT) structureMASUOKA FUJIO·Filed 2011·Granted Oct 6, 2015·9 cites·11 claims
- 0489US8486785B2Surround gate CMOS semiconductor deviceMASUOKA FUJIO·Filed 2011·Granted Jul 16, 2013·12 cites·10 claims
- 0588US7824968B2LDMOS using a combination of enhanced dielectric stress layer and dummy gatesCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Nov 2, 2010·14 cites·44 claims
- 0678US8293614B2High performance LDMOS device having enhanced dielectric strain layerCHU SANFORD·Filed 2011·Granted Oct 23, 2012·5 cites·10 claims
- 0776US8609494B2Surround gate CMOS semiconductor deviceUNISANTIS ELECT SINGAPORE PTE·Filed 2013·Granted Dec 17, 2013·4 cites·2 claims
- 0874US7951680B2Integrated circuit system employing an elevated drainGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted May 31, 2011·5 cites·20 claims
- 0971US8334567B2LDMOS using a combination of enhanced dielectric stress layer and dummy gatesCHU SANFORD·Filed 2010·Granted Dec 18, 2012·3 cites·20 claims
- 1069US8410553B2Semiconductor structure including high voltage deviceKOO JEOUNG MO·Filed 2010·Granted Apr 2, 2013·3 cites·20 claims
- 1169US7253483B2Semiconductor device layout and channeling implant processCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Aug 7, 2007·2 cites·23 claims
- 1264US9490362B2Semiconductor device production method and semiconductor deviceUNISANTIS ELECT SINGAPORE PTE·Filed 2015·Granted Nov 8, 2016·1 cites·4 claims
- 1360US8163621B2High performance LDMOS device having enhanced dielectric strain layerCHU SANFORD·Filed 2008·Granted Apr 24, 2012·2 cites·8 claims
- 1459US2024206146A1Method for producing pillar-shaped semiconductor deviceUNISANTIS ELECT SINGAPORE PTE·Filed 2024·Application pending·0 cites
- 1557US7867862B2Semiconductor structure including high voltage deviceCHARTERED SEMICONDUCTOR MFG·Filed 2007·Granted Jan 11, 2011·1 cites·19 claims
- 1655US7101743B2Low cost source drain elevation through poly amorphizing implant technologyCHARTERED SEMICONDUCTOR MFG L·Filed 2004·Granted Sep 5, 2006·8 cites·13 claims
- 1752US2023058135A1Pillar-shaped semiconductor device and method for producing the sameUNISANTIS ELECT SINGAPORE PTE·Filed 2022·Application pending·0 cites
- 1851US7573099B2Semiconductor device layout and channeling implant processCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Aug 11, 2009·0 cites·21 claims
- 1951US6972236B2Semiconductor device layout and channeling implant processCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Dec 6, 2005·2 cites·13 claims
- 2051US2016308013A1Semiconductor device and production methodUNISANTIS ELECT SINGAPORE PTE·Filed 2016·Application pending·0 cites
- 2149US2015357428A1Surrounding gate transistor (sgt) structureUNISANTIS ELECT SINGAPORE PTE·Filed 2015·Application pending·0 cites
- 2248US9666688B2Semiconductor device production method and semiconductor deviceUNISANTIS ELECT SINGAPORE PTE·Filed 2016·Granted May 30, 2017·0 cites·5 claims
- 2344US7888752B2Structure and method to form source and drain regions over doped depletion regionsGLOBALFOUNDRIES SG PTE LTD·Filed 2007·Granted Feb 15, 2011·0 cites·18 claims
- 2443US2010109045A1Integrated circuit system employing stress-engineered layersCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 2542US7259072B2Shallow low energy ion implantation into pad oxide for improving threshold voltage stabilityCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Aug 21, 2007·1 cites·16 claims
- 2637US9269770B2Integrated circuit system with double doped drain transistorLI YISUO·Filed 2007·Granted Feb 23, 2016·0 cites·20 claims
- 2737US7202133B2Structure and method to form source and drain regions over doped depletion regionsCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Apr 10, 2007·1 cites·27 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →