Inventor · disambiguated record
Yung-Chi Lin
Also filed as: LIN YUNG-CHI
79 granted patents·35 pending applications·1,509 citations·filing 1989–2025
99Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD86TAIWAN SEMICONDUCTOR MFG10LIN YUNG-CHI8YU CHEN-HUA2CHANG HUNG-PIN1
Top patents by PatentIndex Score
114 records- 0199US11502072B2Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 15, 2022·7 cites·19 claims
- 0298US11145623B2Integrated circuit packages and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Oct 12, 2021·23 cites·20 claims
- 0398US9425126B2Dummy structure for chip-on-wafer-on-substrateTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Aug 23, 2016·883 cites·20 claims
- 0498US8803316B2TSV structures and methods for forming the sameLIN YUNG-CHI·Filed 2011·Granted Aug 12, 2014·381 cites·20 claims
- 0597US12266612B2Method for forming a semiconductor device including forming a first interconnect structure on one side of a substrate having first metal feature closer the substrate than second metal feature and forming first and second tsv on other side of substrate connecting to the metal featuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Apr 1, 2025·2 cites·20 claims
- 0697US11855021B2Semiconductor structure with through substrate vias and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Dec 26, 2023·3 cites·20 claims
- 0797US8866301B2Package systems having interposers with interconnection structuresLIN YUNG-CHI·Filed 2010·Granted Oct 21, 2014·33 cites·21 claims
- 0896US12015008B2Wafer bonding methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jun 18, 2024·2 cites·20 claims
- 0996US11855067B2Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Dec 26, 2023·2 cites·20 claims
- 1096US9773768B2Method and structure of three-dimensional chip stackingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Sep 26, 2017·12 cites·20 claims
- 1196US8338939B2TSV formation processes using TSV-last approachLIN JING-CHENG·Filed 2010·Granted Dec 25, 2012·22 cites·20 claims
- 1295US11728314B2Methods of forming integrated circuit packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Aug 15, 2023·2 cites·20 claims
- 1395US9847255B2TSV formation processes using TSV-last approachTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 19, 2017·9 cites·20 claims
- 1493US11854990B2Method for forming a semiconductor device having TSV formed through a silicon interposer and a second silicon substrate with cavity covering a second dieTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Dec 26, 2023·2 cites·20 claims
- 1593US11101240B2Isolation bonding film for semiconductor packages and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Aug 24, 2021·7 cites·20 claims
- 1693US8956966B2TSV structures and methods for forming the sameTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Feb 17, 2015·11 cites·20 claims
- 1790US11437344B2Wafer bonding methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 6, 2022·2 cites·20 claims
- 1890US10297550B23D IC architecture with interposer and interconnect structure for bonding diesHU HSIEN PIN·Filed 2010·Granted May 21, 2019·10 cites·20 claims
- 1990US8580682B2Cost-effective TSV formationYANG KU-FENG·Filed 2010·Granted Nov 12, 2013·11 cites·18 claims
- 2089US10867985B2Method and structure of three-dimensional chip stackingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 15, 2020·4 cites·20 claims
- 2189US8946742B2Semiconductor package with through silicon viasYU CHEN-HUA·Filed 2010·Granted Feb 3, 2015·7 cites·20 claims
- 2288US9449898B2Semiconductor device having backside interconnect structure through substrate via and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Sep 20, 2016·6 cites·20 claims
- 2387US9252110B2Interconnect structure and method of forming sameTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Feb 2, 2016·6 cites·20 claims
- 2486US2024387393A1Method for Forming a Semiconductor Device Having TSV Formed Through a Silicon Interposer and a Second Silicon Substrate with Cavity Covering a Second DieTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2585US10510641B2Semiconductor device having backside interconnect structure on through substrate via and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 17, 2019·3 cites·18 claims
- 2685US9425067B2Method for forming package systems having interposersTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 23, 2016·3 cites·20 claims
- 2785US2025266325A1Semiconductor Device Having Backside Interconnect Structure on Through Substrate ViaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2884US12374651B2Wafer bonding methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jul 29, 2025·0 cites·20 claims
- 2984US12322680B2Semiconductor device having backside interconnect structure on through substrate viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 3, 2025·0 cites·20 claims
- 3083US11304290B2Semiconductor structures and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 12, 2022·4 cites·20 claims
- 3183US2025316644A1Wafer bonding methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3283US2024387465A1Integrated circuit packages and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 3382US12261151B2Integrated circuit packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Mar 25, 2025·0 cites·20 claims
- 3482US8772945B2Through silicon via with embedded barrier padLIN YUNG-CHI·Filed 2012·Granted Jul 8, 2014·6 cites·20 claims
- 3581US9754831B2Dummy structure for chip-on-wafer-on-substrateTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Sep 5, 2017·3 cites·20 claims
- 3680US12087732B2Isolation bonding film for semiconductor packages and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Sep 10, 2024·0 cites·20 claims
- 3780US10515940B2Method and structure of three-dimensional chip stackingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Dec 24, 2019·2 cites·20 claims
- 3880US2025349553A1Stealth patterning formation for bonding improvementTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3979US9343390B2TSV formation processes using TSV-last approachTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted May 17, 2016·3 cites·17 claims
- 4078US9112007B2Through via structure and methodLIN YUNG-CHI·Filed 2012·Granted Aug 18, 2015·3 cites·13 claims
- 4177US11056419B2Semiconductor device having backside interconnect structure on through substrate via and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jul 6, 2021·1 cites·19 claims
- 4276US9171815B2Method of forming package systems having interposersTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Oct 27, 2015·2 cites·20 claims
- 4376US2025343162A1Warpage modulation through implantation and the structures thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4475US11823979B2Method of forming semiconductor device having backside interconnect structure on through substrate viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 21, 2023·0 cites·20 claims
- 4575US9418933B2Through-substrate via formation with improved topography controlTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 16, 2016·2 cites·19 claims
- 4675US2025343164A1Semiconductor structure with stress relief layer and the methods forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4775US2025343186A1Bond features for reducing non-bond and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4875US2025336687A1Packages with implantationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4975US2025343165A1Packaged device with air gap and methods of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 5075US2025343123A1Integrated circuit package and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
Showing the top 50 of 114 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Yung-Chi Lin files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →