Method of forming semiconductor device having backside interconnect structure on through substrate via

Abstract

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

What is claimed is: 
     
       1. A method, comprising:
 forming a conductor extending from a frontside of a wafer toward a backside of the wafer; 
 thinning back the backside of the wafer to expose an end of the conductor protruding from the backside of the wafer; 
 covering the backside of the wafer with an isolation film; 
 patterning the exposed end of the conductor into a concave surface; 
 forming a conductive layer within the concave surface, the conductive layer having a concave surface; 
 patterning the conductive layer; 
 covering the conductive layer with a passivation layer; and 
 patterning the passivation layer. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming one or more transistors on the frontside of the wafer; 
 covering the one or more transistors with an isolation layer; 
 forming over the isolation layer a stack of dielectric layers, each of the stack of dielectric layers having a metallization layer formed therein; 
 forming a contact on a topmost one of the metallization layers; and 
 forming a conductive bump on the contact. 
 
     
     
       3. The method of  claim 1 , further comprising forming an opening extending through the isolation film. 
     
     
       4. The method of  claim 1 , wherein the step of covering the backside of the wafer with the isolation film includes depositing a dielectric material on the backside of the wafer and on the exposed end of the conductor. 
     
     
       5. The method of  claim 4 , further comprising leveling a top surface of the dielectric material to be level with a top surface of the exposed end of the conductor. 
     
     
       6. The method of  claim 1 , wherein the step of patterning the exposed end of the conductor into the concave surface includes dry etching the exposed end of the conductor using an etchant selected from the group consisting of HBr/O 2 , HBr/Cl 2 /O 2 , SF 6 /CL 2 , and S 6  plasma. 
     
     
       7. The method of  claim 1 , wherein the step of patterning the exposed end of the conductor into the concave surface includes etching the exposed end of the conductor until a topmost surface of the conductor, at a lowest point of the topmost surface of the conductor, is below the topmost surface of the isolation film in a range of from about 1000 Å to about 2 μm. 
     
     
       8. The method of  claim 1 , wherein the step of patterning the exposed end of the conductor into the concave surface further includes patterning a portion of the isolation film into a concave surface. 
     
     
       9. The method of  claim 1 , wherein the step of forming the conductive layer within the concave surface includes conformally depositing the conductive layer such that a portion of a topmost surface of the conductive layer deposited on the concave surface of the conductor is lower than a portion of topmost surface of the conductive layer deposited on the isolation film. 
     
     
       10. A method comprising:
 forming a conductor extending partially through a substrate; 
 thinning the substrate to expose an end of the conductor; 
 forming an isolation film on the substrate, leaving the end of the conductor exposed; 
 etching the end of the conductor to form a concave surface; 
 conformally depositing a conductive layer on the concave surface; 
 patterning the conductive layer; 
 covering the patterned conductive layer with a passivation layer; and 
 patterning the passivation layer to expose a portion of the patterned conductive layer. 
 
     
     
       11. The method of  claim 10 , wherein the step of forming the isolation film on the substrate, leaving the end of the conductor exposed includes depositing the isolation film covering the end of the conductor and then removing a portion of the isolation film. 
     
     
       12. The method of  claim 10 , wherein the step of etching the end of the conductor to form the concave surface includes dry etching the end of the conductor. 
     
     
       13. The method of  claim 12 , wherein the dry etching includes an etching selected from the group consisting of HBr/O 2 , HBr/Cl 2 /O 2 , S 6  plasma. 
     
     
       14. The method of  claim 10 , wherein the step of etching the end of the conductor to form the concave surface continues until a lowest point of the concave surface is below a topmost surface of the isolation film by a distance of about 1000 Å to about 2 μm. 
     
     
       15. The method of  claim 10 , wherein the step of conformally depositing the conductive layer on the concave surface includes simultaneously depositing a planar portion of the conductive layer over the isolation film. 
     
     
       16. A method comprising:
 forming a through-substrate via extending from a first side to a second side of a semiconductor substrate opposite the first side; 
 forming an isolation structure on the second side of the semiconductor substrate that leaves exposed a curved surface of the through-substrate via; 
 depositing a conductive layer comprising a first portion formed on the curved surface of the through substrate via and a second portion formed on the isolation structure; and 
 depositing a passivation layer on the conductive layer, wherein the passivation layer comprises a concave portion on the first portion of the conductive layer. 
 
     
     
       17. The method of  claim 16 , wherein the curved surface is a concave surface. 
     
     
       18. The method of  claim 16 , further comprising forming an opening in the passivation layer, the opening aligned with the second portion of the conductive layer. 
     
     
       19. The method of  claim 16 , wherein the curved surface extends lower than a topmost surface of the isolation structure. 
     
     
       20. The method of  claim 16 , wherein the first portion of the conductive layer is deposited conformally to the curved surface of the through-substrate via.