Semiconductor structures and methods

Abstract

A method includes attaching a substrate to a carrier, aligning external connectors on a first surface of a first semiconductor package to first conductive pads on a first surface of the substrate facing away from the carrier, and performing a reflow process, where a difference in coefficients of thermal expansion (CTEs) between the substrate and the carrier causes a first shape for the first surface of the substrate during the reflow process, where differences among CTEs of materials of the first semiconductor package causes a second shape for the first surface of the first semiconductor package during the reflow process, and wherein the first shape substantially matches the second shape. The method further includes removing the carrier from the substrate after the reflow process.

What is claimed is: 
     
       1. A method comprising:
 attaching a first surface of a substrate to a first surface of a carrier, wherein the first surface of the substrate extends along and contacts the first surface of the carrier, wherein a structure and materials of the carrier comprise: 
 a first material extending continuously from the first surface of the carrier to a second surface of the carrier furthest from the substrate; 
 a second material extending continuously from the first surface of the carrier to the second surface of the carrier, wherein the second material is different from the first material and is disposed laterally adjacent to the first material, wherein the first material and the second material of the carrier are chosen to increase a warpage of the substrate at a reflow temperature compared with a room temperature; and 
 a multi-layer structure laterally between and in contact with the first material and the second material, wherein the multi-layer structure extends continuously from the first surface of the carrier to the second surface of the carrier, wherein the multi-layer structure comprises:
 a first sublayer; and 
 a second sublayer over the first sublayer, wherein sidewalls of the first sublayer are aligned with respective sidewalls of the second sublayer, wherein each of the first material, the second material, the first sublayer, and the second sublayer comprises a different material, wherein the first material, the second material, and the multi-layer structure have a coplanar upper surface and a coplanar lower surface; 
 
 aligning external connectors on a first surface of a first semiconductor package to first conductive pads on a second surface of the substrate facing away from the carrier; 
 performing a reflow process, wherein a difference in coefficients of thermal expansion (CTEs) between the substrate and the carrier causes a first shape for the second surface of the substrate during the reflow process, wherein differences among CTEs of materials of the first semiconductor package causes a second shape for the first surface of the first semiconductor package during the reflow process, and wherein the first shape substantially matches the second shape; 
 removing the carrier from the substrate after the reflow process, where the carrier is intact after removing the carrier; 
 after removing the carrier, attaching a first surface of another substrate to the first surface of the carrier; and 
 performing another reflow process to bond a second semiconductor package to a second surface of the another substrate. 
 
     
     
       2. The method of  claim 1 , wherein the carrier is an electro-static chuck, wherein the structure and the materials of the carrier are designed specifically to induce a warpage in the substrate during the reflow process such that the first shape of the substrate substantially matches the second shape of the first semiconductor package. 
     
     
       3. The method of  claim 1 , wherein the substrate is a printed circuit board (PCB). 
     
     
       4. The method of  claim 3 , wherein the first shape and the second shape are curved shapes. 
     
     
       5. The method of  claim 1 , wherein performing the reflow process physically and electrically couple the first semiconductor package to the substrate. 
     
     
       6. The method of  claim 1 , further comprising before performing the reflow process, aligning external connectors of a second semiconductor package to second conductive pads on the second surface of the substrate, wherein the reflow process physically and electrically couples the first semiconductor package and the second semiconductor package to the substrate. 
     
     
       7. The method of  claim 1 , wherein the substrate has a rectangular shape, a square shape, a polygon shape, or a circular shape. 
     
     
       8. A method comprising:
 tuning a coefficient of thermal expansion (CTE) of a carrier, wherein tuning the CTE of the carrier comprises:
 forming a first segment of the carrier using a first material having a first CTE, the first material extending continuously from a first surface of the carrier to a second surface of the carrier opposing the first surface; 
 forming a second segment of the carrier using a second material having a second CTE different from the first CTE, the second material extending continuously from the first surface of the carrier to the second surface of the carrier; and 
 forming a multi-layer structure laterally adjacent to the first segment and the second segment, wherein the multi-layer structure, the first segment, and the second segment have a same thickness, wherein the multi-layer structure comprises a plurality of sublayers having a same width, wherein each of the first segment, the second segment, and the plurality of sublayers has a different CTE; 
 
 attaching a first side of a substrate to the first surface of the carrier, the substrate having conductive pads on a second side of the substrate opposing the first side, wherein the first side of the substrate contacts and extends along the first surface of the carrier, wherein the second surface of the carrier is a surface of the carrier furthest from the substrate; 
 placing a semiconductor package over the second side of the substrate, wherein external connectors on a first side of the semiconductor package facing the substrate are aligned with respective conductive pads of the substrate; 
 heating the substrate, the carrier, and the semiconductor package, wherein the first side of the semiconductor package has a first curved shape during the heating, wherein the CTE of the carrier is tuned with respect to a CTE of the substrate such that during the heating, a warpage of the substrate is increased compared with that at a room temperature, and the second side of the substrate has a second curved shape, and wherein the first curved shape substantially matches the second curved shape; 
 removing the carrier from the substrate after the heating, wherein the carrier is intact after removing the carrier; and 
 after removing the carrier, attaching a first side of another substrate to the first surface of the carrier. 
 
     
     
       9. The method of  claim 8 , wherein the external connectors of the semiconductor package contact respective conductive pads of the substrate during the heating. 
     
     
       10. The method of  claim 8 , further comprising:
 analyzing a warpage of the semiconductor package at a heating temperature; and 
 determining the first curved shape of the first side of the semiconductor package at the heating temperature. 
 
     
     
       11. The method of  claim 8 , wherein the substrate is a printed circuit board. 
     
     
       12. The method of  claim 8 , wherein the semiconductor package comprises:
 a semiconductor die; 
 a molding material around the semiconductor die; 
 conductive features electrically coupled to the semiconductor die and extending beyond boundaries of the semiconductor die; and 
 the external connectors electrically coupled to the conductive features, wherein the conductive features are between the semiconductor die and the external connectors. 
 
     
     
       13. The method of  claim 12 , wherein the conductive features are redistribution layers (RDLs) of a redistribution structure between the semiconductor die and the external connectors. 
     
     
       14. The method of  claim 12 , wherein the conductive features are vias of an interposer between the semiconductor die and the external connectors. 
     
     
       15. A method comprising:
 attaching a first side of a substrate to a first surface of a carrier, wherein the first side of the substrate contacts and extends along the first surface of the carrier, wherein the carrier comprises:
 a first segment formed of a first material, the first material extending continuously from the first surface of the carrier to an opposing second surface of the carrier distal from the substrate; 
 a second segment formed of a second material different from the first material, the second segment being laterally adjacent to the first segment and having a same thickness as the first segment; and 
 a multi-layer structure laterally adjacent to the first segment and the second segment, wherein the multi-layer structure, the first segment, and the second segment have a coplanar upper surface and a coplanar lower surface, wherein the multi-layer structure comprises a plurality of sublayers having a same width, wherein each of the first segment, the second segment, and the plurality of sublayers has a different coefficient of thermal expansion; 
 
 bonding a semiconductor package to a second side of the substrate opposing the first side at a bonding temperature, wherein a first side of the semiconductor package facing the substrate has a first curved shape at the bonding temperature, wherein differences of coefficients of thermal expansion (CTEs) between the carrier and the substrate increase a warpage of the substrate at the bonding temperature compared with a room temperature, and result in a second curved shape for the second side of the substrate at the bonding temperature, and wherein the first curved shape matches the second curved shape; 
 removing the carrier from the substrate after the bonding, where the carrier is intact after removing the carrier; and 
 after removing the carrier, attaching another substrate to the carrier for bonding with another semiconductor package. 
 
     
     
       16. The method of  claim 15 , wherein bonding the semiconductor package comprises bonding external connectors of the semiconductor package to conductive pads disposed on the second side of the substrate, wherein the external connectors of the semiconductor package contact respective conductive pads of the substrate during the bonding. 
     
     
       17. The method of  claim 15 , further comprising analyzing a warpage of the semiconductor package at the bonding temperature. 
     
     
       18. The method of  claim 17 , wherein the analyzing comprises measuring and analyzing moiré patterns of the semiconductor package. 
     
     
       19. The method of  claim 15 , wherein a first sidewall of the first segment contacts and extends long a second sidewall of the second segment. 
     
     
       20. The method of  claim 15 , wherein the carrier is a chuck, and wherein the chuck is designed for the semiconductor package such that the chuck generates the second curved shape for the second side of the substrate at the bonding temperature.