Fin-type field effect transistor structure and manufacturing method thereof

Abstract

A fin-type field effect transistor comprising a substrate, at least one gate stack, spacers and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins comprise channel portions and flank portions beside the channel portions, the flank portions and the channel portions of the fins are protruded from the insulators, the flank portions of the fins and the channel portions of the fins have substantially a same height from top surfaces of the insulators, and each of the flank portions of the fins has a top surface and side surfaces adjoining the top surface. The at least one gate stack is disposed over the substrate, disposed on the insulators and over the channel portions of the fins. The spacers are disposed on the side surfaces of the flank portions of the fins. The epitaxy material portions are located above the top surfaces of the flank portions of the fins.

What is claimed is: 
     
       1. A fin-type field effect transistor, comprising:
 a substrate having fins and insulators located between the fins, wherein the fins comprise channel portions and flank portions beside the channel portions, the flank portions and the channel portions of the fins are protruded from the insulators, the flank portions of the fins and the channel portions of the fins have substantially a same height from top surfaces of the insulators, and each of the flank portions of the fins has a top surface and side surfaces adjoining the top surface; 
 at least one gate stack, disposed over the substrate, disposed on the insulators and over the channel portions of the fins; 
 spacers, disposed on the side surfaces of the flank portions of the fins; and 
 epitaxy material portions, located above the top surfaces of the flank portions of the fins. 
 
     
     
       2. The transistor of  claim 1 , wherein the epitaxy material portions cover the top surfaces of the flank portions without contacting the spacers. 
     
     
       3. The transistor of  claim 1 , wherein the spacers cover end surfaces of the fins without covering the top surfaces of the flank portions. 
     
     
       4. The transistor of  claim 1 , wherein a total height of the flank portion and the corresponding epitaxy material portion is equal to or less than a height of the at least one gate stack from the top surface of the insulator. 
     
     
       5. The transistor of  claim 1 , wherein the at least one gate stack comprises:
 a gate dielectric layer, disposed on the insulators and covering the channel portions of the fins; 
 a gate electrode layer, disposed on the gate dielectric layer; and 
 gate spacers, wherein the gate dielectric layer and the gate electrode layer are located between the gate spacers. 
 
     
     
       6. The transistor of  claim 5 , wherein a material of spacers is the same as a material of gate spacers. 
     
     
       7. The transistor of  claim 6 , wherein the material of the spacers and the material of gate spacers comprise silicon nitride, silicon carbon oxynitride (SiCON), silicon carbonitride (SiCN) or combinations thereof. 
     
     
       8. A fin-type field effect transistor, comprising:
 a substrate having fins and insulators between the fins, wherein the fins comprise flank portions and channel portions sandwiched between the flank portions, and the fins have end surfaces; 
 at least one gate stack, disposed across and over the channel portions of the fins and disposed on the insulators; 
 spacers, disposed on side surfaces of the flank portions of the fins and the end surfaces of the fins; and 
 epitaxy material portions, disposed on the flank portions, wherein the flank portions and the channel portions of the fins are protruded from top surfaces of the insulators and have substantially a same height from the top surfaces of the insulators, and the epitaxy material portions are protruded from top surfaces of the flank portions. 
 
     
     
       9. The transistor of  claim 8 , wherein the flank portions of the fins and the spacers have substantially a same height from the top surfaces of the insulators. 
     
     
       10. The transistor of  claim 8 , wherein a total height of the flank portion and the corresponding epitaxy material portion is equal to or less than a height of the at least one gate stack. 
     
     
       11. The transistor of  claim 8 , wherein the epitaxy material portions are located above top surfaces of the channel portions. 
     
     
       12. The transistor of  claim 8 , wherein the at least one gate stack comprises a replacement metal gate. 
     
     
       13. The transistor of  claim 8 , wherein the at least one gate stack comprises:
 a gate dielectric layer, disposed on the insulators and covering the channel portions of the fins; 
 a gate electrode layer, disposed on the gate dielectric layer; and 
 gate spacers, wherein the gate dielectric layer and the gate electrode layer are located between the gate spacers. 
 
     
     
       14. The transistor of  claim 8 , wherein the epitaxy material portions disposed on the flank portions of one fin merge with the epitaxy material portions disposed on the flank portions of another adjacent fin. 
     
     
       15. A method for forming a fin-type field effect transistor, comprising:
 providing a substrate; 
 patterning the substrate to form trenches in the substrate and fins between the trenches, wherein the fins comprise channel portions and flank portions; 
 forming insulators in the trenches of the substrate; 
 forming at least one stack strip structure over the substrate and on the insulators; 
 forming a spacer material layer covering the at least one stack strip structure and covering the flank portions; 
 removing the spacer material layer to expose top surfaces of the flank portions and a top surface of the at least one stack strip structure to form spacers on side surfaces of the flank portions and form gate spacers on side surfaces of the at least one stack strip structure; 
 forming epitaxy material portions directly from the exposed top surfaces of the flank portions; 
 removing the at least one stack strip structure; and 
 forming at least one gate stack on the insulators and covering the channel portions of the fins. 
 
     
     
       16. The method of  claim 15 , wherein removing the spacer material layer further comprises removing the spacer material layer from the top surfaces of the flank portions without removing the spacer material layer from the side surfaces of the flank portions and without removing the spacer material layer from end surfaces of the fins. 
     
     
       17. The method of  claim 15 , wherein removing the spacer material layer further comprises removing the spacer material layer from top surfaces of the insulators. 
     
     
       18. The method of  claim 15 , wherein removing the spacer material layer further comprises removing the spacer material layer from the top surfaces of the flank portions without removing the flank portions, so that the flank portions and the channel portions of the fins have substantially a same height from top surfaces of the insulators after removing the spacer material layer. 
     
     
       19. The method of  claim 15 , wherein forming epitaxy material portions comprises performing a selective epitaxy growth process to form the epitaxy material portions directly from the exposed top surfaces of the flank portions. 
     
     
       20. The method of  claim 15 , wherein removing the spacer material layer comprises performing an anisotropic etching process.