Power semiconductor transistor having fully depleted channel region

Abstract

A power semiconductor transistor includes a trench extending into a semiconductor body along a vertical direction and having first and second trench sidewalls and a trench bottom, an electrode in the trench electrically insulated from the semiconductor body, drift and source regions of a first conductivity type, a semiconductor channel region of a second conductivity type laterally adjacent the first trench sidewall and separating the source and drift regions, and a guidance zone. The guidance zone includes a bar section of the second conductivity type extending along the second trench sidewall or along a sidewall of another trench in the vertical direction to a depth in the semiconductor body deeper than the trench bottom, and a plateau section of the second conductivity type adjoining the bar section and extending under the trench bottom towards the semiconductor channel region. The plateau section has at least one opening below the channel region.

What is claimed is: 
     
       1. A power semiconductor transistor, comprising:
 a semiconductor body coupled to a load terminal; 
 a drift region of a first conductivity type in the semiconductor body; 
 a trench extending into the semiconductor body along a vertical direction and having first and second trench sidewalls and a trench bottom; 
 an electrode in the trench and electrically insulated from the semiconductor body; 
 a source region of the first conductivity type laterally adjacent the first trench sidewall and electrically connected to the load terminal; 
 a semiconductor channel region of a second conductivity type laterally adjacent the first trench sidewall and separating the source region from the drift region; and 
 a guidance zone electrically connected to the load terminal, 
 wherein the guidance zone comprises a bar section of the second conductivity type extending along the second trench sidewall or along a sidewall of another trench in the vertical direction to a depth in the semiconductor body deeper than the trench bottom, 
 wherein the guidance zone comprises a plateau section of the second conductivity type adjoining the bar section and extending under the trench bottom towards the semiconductor channel region, 
 wherein the plateau section has at least one opening below the semiconductor channel region 
 wherein the power semiconductor transistor is devoid of a source region in contact with the guidance zone so that the guidance zone does not provide a current path in a forward direction. 
 
     
     
       2. The power semiconductor transistor of  claim 1 , wherein the plateau section has a plurality of openings aligned below the semiconductor channel region. 
     
     
       3. The power semiconductor transistor of  claim 2 , wherein the plurality of openings is spatially displaced from each other such that there are regions below the semiconductor channel region that are covered by the plateau section. 
     
     
       4. The power semiconductor transistor of  claim 1 , wherein the at least one opening of the plateau section is filled by the drift region. 
     
     
       5. The power semiconductor transistor of  claim 1 , wherein a dopant concentration of the plateau section is substantially constant along each of first and second transverse lateral directions except for the at least one opening. 
     
     
       6. The power semiconductor transistor of  claim 1 , wherein the plateau section has a single opening aligned below the semiconductor channel region so that the plateau section is completely interrupted below the semiconductor channel region. 
     
     
       7. The power semiconductor transistor of  claim 6 , wherein the interruption in the plateau section below the semiconductor channel region is filled by the drift region. 
     
     
       8. The power semiconductor transistor of  claim 6 , wherein the interruption in the plateau section below the semiconductor channel region has a width which exceeds a width of the source region above the plateau section in a first lateral direction. 
     
     
       9. The power semiconductor transistor of  claim 1 , wherein below the semiconductor channel region the plateau section has one or more openings that are covered by the drift region and one or more regions having a locally reduced dopant concentration as compared to remaining parts of the plateau section. 
     
     
       10. The power semiconductor transistor of  claim 9 , wherein the dopant concentration of the one or more regions having a locally reduced dopant concentration is less than 50% of a dopant concentration of the remaining parts of the plateau section. 
     
     
       11. The power semiconductor transistor of  claim 1 , wherein the plateau section has a substantially constant dopant concentration along a first lateral direction when traversing below the semiconductor channel region. 
     
     
       12. The power semiconductor transistor of  claim 1 , wherein the at least one opening of the plateau section is laterally aligned to the semiconductor channel region. 
     
     
       13. The power semiconductor transistor of  claim 1 , wherein the at least one opening of the plateau section has the same width of the semiconductor channel region in at least a first lateral direction. 
     
     
       14. The power semiconductor transistor of  claim 1 , wherein the at least one opening of the plateau section has the same width of the semiconductor channel region in first and second transverse lateral directions. 
     
     
       15. The power semiconductor transistor of  claim 14 , wherein the width of the at least one opening of the plateau section in the first lateral direction is different than the width of the at least one opening of the plateau section in the second lateral direction. 
     
     
       16. The power semiconductor transistor of  claim 1 , wherein the guidance zone is configured to guide an electrical potential of the load terminal to lateral extremities of the plateau section and to a vertical extremity of the plateau section. 
     
     
       17. The power semiconductor transistor of  claim 1 , wherein, below the trench bottom, the trench and the guidance zone have a common lateral extension range of at least 75% of a total extension of the trench bottom along a first lateral direction. 
     
     
       18. The power semiconductor transistor of  claim 1 , wherein the plateau section is spaced apart from the trench bottom in the vertical direction. 
     
     
       19. The power semiconductor transistor of  claim 1 , wherein the plateau section has a plurality of openings aligned below the semiconductor channel region in a widthwise direction of the semiconductor channel region. 
     
     
       20. A power semiconductor transistor, comprising:
 a semiconductor body coupled to a first load terminal; 
 a semiconductor drift region in the semiconductor body and having dopants of a first conductivity type; 
 a first trench extending into the semiconductor body along a vertical direction, the first trench including a first control electrode electrically insulated from the semiconductor body by a first insulator, the first trench being laterally confined by two first trench sidewalls and vertically confined by a first trench bottom; 
 a second trench extending into the semiconductor body along the vertical direction, the second trench being laterally confined by two second trench sidewalls and vertically confined by a second trench bottom; 
 a mesa region arranged between the first and second trenches and comprising a first source region arranged laterally adjacent to one of the first trench sidewalls and being electrically connected to the first load terminal, and a first semiconductor channel region arranged laterally adjacent to the same first trench sidewall as the first source region, the first semiconductor channel region having dopants of a second conductivity type and isolating the first source region from the drift region; 
 a portion of a contiguous plateau region of the second conductivity type arranged in the semiconductor drift region and extending below both the first trench bottom and the second trench bottom and below the first semiconductor channel region and the first source region, 
 wherein the contiguous plateau region has a plurality of openings aligned below the first semiconductor channel region in a widthwise direction of the first semiconductor channel region. 
 
     
     
       21. The method of  claim 20 , wherein the power semiconductor transistor is devoid of a source region in contact with the contiguous plateau region so that the contiguous plateau region does not provide a current path in a forward direction. 
     
     
       22. A method of manufacturing a power semiconductor transistor, the method comprising:
 coupling a semiconductor body to a load terminal; 
 forming a drift region of a first conductivity type in the semiconductor body; 
 forming a trench extending into the semiconductor body along a vertical direction and having first and second trench sidewalls and a trench bottom; 
 forming an electrode in the trench and electrically insulated from the semiconductor body; 
 forming a source region of the first conductivity type laterally adjacent the first trench sidewall and electrically connected to the load terminal; 
 forming a semiconductor channel region of a second conductivity type laterally adjacent the first trench sidewall and separating the source region from the drift region; and 
 forming a guidance zone electrically connected to the load terminal, 
 wherein forming the guidance zone comprises:
 forming a bar section of the second conductivity type extending along the second trench sidewall or along a sidewall of another trench in the vertical direction to a depth in the semiconductor body deeper than the trench bottom; and 
 forming a plateau section of the second conductivity type adjoining the bar section and extending under the trench bottom towards the semiconductor channel region, the plateau section having a plurality of openings aligned below the semiconductor channel region in a widthwise direction of the semiconductor channel region. 
 
 
     
     
       23. The method of  claim 22 , wherein the power semiconductor transistor is devoid of a source region in contact with the guidance zone so that the guidance zone does not provide a current path in a forward direction.