Power semiconductor device having fully depleted channel regions

Abstract

A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.

The invention claimed is: 
     
       1. A power semiconductor device, comprising:
 a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current; 
 a first cell and a second cell, each being electrically connected to the first load terminal structure on the one side and electrically connected to a drift region of the semiconductor body on the other side, the drift region having a first conductivity type; 
 a first mesa included in the first cell, the first mesa including: a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region; the first cell being configured to induce a load current path in the first channel region in a conducting state; 
 a second mesa included in the second cell, the second mesa including: a second port region having the second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region; 
 each of the first mesa and the second mesa being spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by a first insulation structure and exhibiting a total extension of less than 100 nm in said direction; 
 a further port region comprising an emitter of the second conductivity type being electrically connected to the second load terminal structure, 
 wherein the power semiconductor device further comprises a third cell being electrically connected to the second load terminal structure on the one side and electrically connected to the drift region on the other side; wherein the third cell includes a third mesa comprising: a third port region having the first conductivity type and being electrically connected to the second load terminal structure; a third channel region being coupled to the drift region; and a third control electrode being insulated from the third mesa by a second insulation structure. 
 
     
     
       2. The power semiconductor device of  claim 1 , wherein the first and second cells are configured to fully deplete the first and second channel regions of mobile charge carriers of the second conductivity type in the conducting state. 
     
     
       3. The power semiconductor device of  claim 1 , wherein the third control electrode is configured to induce a conductive channel within the third channel region. 
     
     
       4. The power semiconductor device of  claim 1 , wherein the third cell is configured to fully deplete the third channel region of mobile charge carriers of the second conductivity type in a conducting state of the device. 
     
     
       5. The power semiconductor device of  claim 1 , wherein the third mesa is spatially confined, in a direction perpendicular to a direction of the load current within the third mesa, by the second insulation structure and exhibits a total extension of less than 100 nm in said direction. 
     
     
       6. The power semiconductor device of  claim 1 , further comprising a fourth cell being electrically connected to the second load terminal structure on the one side and electrically connected to the drift region on the other side; wherein the fourth cell includes a fourth mesa comprising: a fourth port region having the second conductivity type and being electrically connected to the second load terminal structure, and a fourth channel region being coupled to the drift region. 
     
     
       7. The semiconductor device of  claim 6 , wherein the fourth port region comprises the further port region. 
     
     
       8. The power semiconductor device of  claim 6 , wherein the fourth cell is configured to induce a conductive channel within the fourth channel region. 
     
     
       9. The power semiconductor device of  claim 6 , wherein the fourth cell is configured to fully deplete the fourth channel region of mobile charge carriers of the second conductivity type. 
     
     
       10. The power semiconductor device of  claim 6 , wherein the fourth cell comprises a fourth control electrode for inducing said conductive channel, and wherein the second insulation structure insulates the fourth control electrode from the fourth mesa. 
     
     
       11. The power semiconductor device of  claim 10 , wherein the fourth control electrode and the third control electrode are connected to each other. 
     
     
       12. The power semiconductor device of  claim 1 , wherein the power semiconductor device is a lateral IGBT. 
     
     
       13. A method of operating a power semiconductor device, wherein the power semiconductor device comprises:
 a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current; 
 a first cell, a second cell, and a third cell, wherein each of the first cell and the second cell are electrically connected to the first load terminal structure on the one side and electrically connected to a drift region of the semiconductor body on the other side, and wherein the third cell is electrically connected to the second load terminal structure on the one side and electrically connected to the drift region on the other side, the drift region having a first conductivity type; 
 a first mesa included in the first cell, the first mesa including: a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region; the first cell being configured to induce a load current path in the first channel region in a conducting state; 
 a second mesa included in the second cell, the second mesa including: a second port region having the second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region; 
 a third mesa included in the third cell, the third mesa including: a third port region having the first conductivity type and being electrically connected to the second load terminal structure, and a third channel region being coupled to the drift region; 
 at least one first control electrode configured to induce the load current path within the first channel region; 
 at least one third control electrode configured to induce a conductive channel within the third channel region; 
 wherein the method comprises: 
 providing a first control signal to the at least one first control electrode, in which the first control electrode induces the load current path within the first channel region; and 
 providing a third control signal to the at least one third control electrode so as to switch the power semiconductor device from a first conducting mode, in which the third control electrode does not induce the conductive channel within the third channel region, to a second conducting mode, in which the third control electrode induces the inversion channel within the third channel region. 
 
     
     
       14. The method of  claim 13 , wherein, in a forward conducting state, the power semiconductor device exhibits a forward voltage between the first load terminal structure and the second load terminal structure while conducting a load current, and wherein:
 in the first forward conducting mode, the forward voltage is in a first forward voltage range, and 
 in the second forward conducting mode, the forward voltage is in a second forward voltage range, wherein the second forward voltage range comprises lower values than the first forward voltage range at least immediately after the switching from the first forward conducting mode to the second forward conducting mode. 
 
     
     
       15. The method of  claim 14 , further comprising providing the third control signal to the at least one third control electrode so as to switch the power semiconductor device from the second forward conducting mode back to the first forward conducting mode before or as soon as said forward voltage has risen to a threshold value. 
     
     
       16. The method of  claim 13 , further comprising providing the first control signal to the at least one first control electrode so as to periodically switch the power semiconductor device between a forward blocking state and a forward conducting state, wherein, in the forward blocking state,
 the first control electrode does not induce a load current path in the first channel region and 
 a voltage that is externally applied between the first load terminal structure and the second load terminal structure is blocked by a space-charge region formed at a transition between the drift region and at least one of the first channel region and the second channel region, 
 
       wherein, within each period of said periodical switching between the forward blocking state and the forward conducting state, said switching from the first forward conducting mode to the second forward conducting mode is carried out with a delay after the power semiconductor device has been switched from the forward blocking state to the forward conducting state, wherein the delay amounts to less than 50 μs. 
     
     
       17. The method of  claim 13 , further comprising:
 providing the first control signal to the at least one first control electrode so as to operate the power semiconductor device in a forward blocking state, wherein:
 the first control electrode does not induce said load current path within the first channel region; and 
 a forward blocking voltage that is externally applied between the first load terminal structure and the second load terminal structure is blocked by a space-charge region formed at a transition between the drift region and at least one of the first channel region and the second channel region; and 
 
 while the power semiconductor device is in the forward blocking state, providing the third control signal to the at least one third control electrode so as to induce said conductive channel within the third channel region. 
 
     
     
       18. The method of  claim 13 , wherein the power semiconductor device further comprises a fourth cell being electrically connected to the second load terminal structure on the one side and electrically connected to the drift region on the other side; wherein the fourth cell includes a fourth mesa comprising: a fourth port region having the second conductivity type and being electrically connected to the second load terminal structure, a fourth channel region being coupled to the drift region, a fourth control electrode for inducing a conductive channel within the fourth channel region, and wherein a second insulation structure insulates the fourth control electrode from the fourth mesa. 
     
     
       19. The method of  claim 18 , wherein the fourth control electrode is electrically connected to the third control electrode and wherein the third control signal is periodically switched between two different voltage values. 
     
     
       20. The method of  claim 19 , wherein the two different voltage values comprise a positive value and a negative value relative to the electric potential of the second load terminal structure.