Power semiconductor device having cells with channel regions of different conductivity types

Abstract

A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected to the first load terminal structure and to a drift region, the drift region having a first conductivity type; a first mesa in the first cell and including: a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region; a second mesa in the second cell and including: a port region of the opposite conductivity type and electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure. The insulation structure houses a control electrode structure, and a guidance electrode arranged between the mesas.

What is claimed is: 
     
       1. A power semiconductor device, comprising:
 a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current; 
 a first cell and a second cell, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type; 
 a first mesa included in the first cell, the first mesa including a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region; and 
 a second mesa included in the second cell, the second mesa including a second port region having a second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region, each of the first mesa and the second mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction, the insulation structure separating a control electrode structure from the first channel region and the second channel region, the control electrode structure being electrically insulated from the first load terminal structure; and 
 a guidance electrode electrically insulated from the control electrode structure and arranged in between the first mesa and the second mesa, 
 wherein the first channel region has the first conductivity type and the second channel region has the second conductivity type. 
 
     
     
       2. The power semiconductor device of  claim 1 , wherein at least one of the first channel region and the second channel region is fully depletable. 
     
     
       3. The power semiconductor device of  claim 1 , wherein the control electrode structure comprises a first control electrode for controlling the first channel region and a second control electrode for controlling the second channel region. 
     
     
       4. The power semiconductor device of  claim 3 , wherein the first control electrode and the second control electrode are arranged separately from each other. 
     
     
       5. The power semiconductor device of  claim 3 , wherein the first control electrode and the second control electrode are implemented as a joint control electrode. 
     
     
       6. The power semiconductor device of  claim 5 , wherein the guidance electrode is formed within the insulation structure and arranged between the first control electrode and the second control electrode. 
     
     
       7. The power semiconductor device of  claim 5 , wherein the guidance electrode is formed within the insulation structure and arranged entirely below the control electrode structure. 
     
     
       8. The power semiconductor device of  claim 1 , wherein the first mesa comprises a semiconductor region arranged below the first channel region and having the first conductivity type and a greater dopant concentration than the drift region. 
     
     
       9. The power semiconductor device of  claim 1 , wherein the semiconductor body comprises a first plateau region and a second plateau region, wherein the first plateau region is in contact with the first channel region, and wherein the second plateau region is arranged between the second channel region and the drift region. 
     
     
       10. The power semiconductor device of  claim 9 , wherein the first plateau region has dopants of the second conductivity type, and wherein the second plateau region is in contact with the second channel region and has dopants of the second conductivity type. 
     
     
       11. The power semiconductor device of  claim 1 , wherein the control electrode structure extends in parallel to each of the first mesa and the second mesa along an extension direction and entirely overlaps with each of the first channel region and the second channel region along the extension direction. 
     
     
       12. The power semiconductor device of  claim 1 , wherein the guidance electrode extends further along the extension direction within the insulation structure than the control electrode structure. 
     
     
       13. The power semiconductor device of  claim 1 , wherein the guidance electrode and the control electrode structure have a common extension range along the direction. 
     
     
       14. The power semiconductor device of  claim 1 , wherein the insulation structure forms a plurality of trenches arranged next to each other, each trench:
 comprising a respective control electrode structure and a respective guidance electrode; and 
 being arranged adjacent to at least one of the first mesa and the second mesa. 
 
     
     
       15. The power semiconductor device of  claim 14 , wherein adjacent two of the plurality of trenches are separated from each other by one of the first mesa and the second mesa. 
     
     
       16. The power semiconductor device of  claim 14 , wherein the second mesa comprises a contact region, the contact region connecting the guidance electrode of one of the adjacent two trenches to the guidance electrode of the other one of the adjacent two trenches. 
     
     
       17. The power semiconductor device of  claim 1 , wherein the guidance electrode has a total lateral extension in a direction between the first and second mesa and a total vertical extension, the total lateral extension being greater than the total vertical extension. 
     
     
       18. The power semiconductor device of  claim 1 , wherein:
 the control electrode structure and at least one of the first mesa and the second mesa have a first common extension range along an extension direction adjacent the insulation structure between the control electrode structure and the at least one of the first mesa and the second mesa; 
 the guidance electrode and the at least one of the first mesa and the second mesa have a second common extension range along the extension direction adjacent the insulation structure between the guidance electrode and the at least one of the first mesa and the second mesa; and 
 the second common extension range is smaller than the first common extension range. 
 
     
     
       19. The power semiconductor device of  claim 1 , wherein the guidance electrode has a total lateral extension in the direction that is greater than a total lateral extension of the control electrode structure. 
     
     
       20. The power semiconductor device of  claim 1 , wherein the effective thickness of the insulation structure insulating the first control electrode structure from the first channel region along the direction is smaller than the effective thickness of the insulation structure insulating the guidance electrode from the semiconductor body along the load current direction.