Etch profile control of polysilicon structures of semiconductor devices

Abstract

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively.

What is claimed is: 
     
       1. A method of forming a fin field effect transistor (finFET) on a substrate, the method comprising:
 forming a fin structure of the finFET on the substrate; 
 forming a first oxide region with a first thickness on a top surface of the fin structure, wherein forming the first oxide region comprises:
 doping the fin structure; 
 depositing an oxide layer on the top surface and sidewalls of the fin structure; and 
 annealing the fin structure and the oxide layer; 
 
 forming a second oxide region with a second thickness on sidewalls on the fin structure, wherein the first thickness is greater than the second thickness, 
 forming a polysilicon structure on the first and second oxide regions; 
 forming a source/drain region on a portion of the fin structure; and 
 replacing the polysilicon structure with a gate structure. 
 
     
     
       2. The method of  claim 1 , wherein doping the fin structure comprises:
 forming an amorphous region on the fin structure, the amorphous region comprising an amorphous material; and 
 doping the amorphous region. 
 
     
     
       3. The method of  claim 1 , wherein forming the first oxide region comprises:
 forming an amorphous silicon region on the fin structure; 
 doping the amorphous silicon region using a fluorine or oxygen dopant, 
 depositing an oxide layer on the amorphous silicon region; and 
 annealing the amorphous silicon region and the oxide layer. 
 
     
     
       4. The method of  claim 1 , wherein the first thickness is greater than the second thickness by a value ranging from about 0.5 nm to about 3 nm. 
     
     
       5. The method of  claim 1 , wherein replacing the polysilicon structure with the gate structure comprises:
 removing the polysilicon structure; 
 etching portions of the oxide region exposed by removing the polysilicon structure; and 
 forming the gate structure on the first and second oxide regions. 
 
     
     
       6. The method of  claim 1 , wherein forming the polysilicon structure on the first and second oxide regions comprises:
 depositing a polysilicon layer on the first and second oxide regions; and 
 etching first and second portions of the polysilicon layer at first and second etch rates, the first etch rate being greater than the second etch rate. 
 
     
     
       7. The method of  claim 2 , wherein forming the amorphous region comprises:
 depositing a layer of insulating material on the fin structure; 
 forming a recessed region within the layer of insulating material and on the fin structure; 
 depositing a layer of the amorphous material on the layer of insulating material to fill the recessed region; and 
 removing portions of the layer of the amorphous material on the layer of insulating material to substantially coplanarize a top surface of the layer of insulating material with top surfaces of other portions of the layer of the amorphous material within the recessed region. 
 
     
     
       8. The method of  claim 2 , wherein a vertical dimension of the amorphous region ranges from about 5 nm to about 20 nm. 
     
     
       9. A method for forming a semiconductor device, comprising:
 forming a first fin structure on a substrate; 
 depositing a first oxide layer on the first fin structure, wherein a first thickness of a first portion of the first oxide layer on a top surface of the first fin structure is greater than a second thickness of a second portion of the first oxide layer on a sidewall of the first fin structure; 
 depositing a first gate electrode on the first oxide layer; 
 forming a second fin structure on the substrate; 
 depositing a second oxide layer on the second fin structure, wherein a first thickness of a first portion of the second oxide layer on a top surface of the second fin structure is substantially equal to a second thickness of a second portion of the second oxide layer on a sidewall of the second fin structure; and 
 depositing a second gate electrode on the second oxide layer. 
 
     
     
       10. The method of  claim 9 , wherein the first thickness of the first portion of the first oxide layer is greater than the second thickness of the second portion of the first oxide layer by a value ranging from about 0.5 nm to about 3 nm. 
     
     
       11. The method of  claim 9 , wherein the first portion of the first oxide layer extends laterally beyond a sidewall of the second portion of the first oxide layer by a value ranging from about 0.1 nm to about 1 nm. 
     
     
       12. The method of  claim 9 , wherein depositing the first and second oxide layers comprises:
 depositing a layer of oxide material on the first and second fin structures, and 
 treating the deposited layer of oxide material with an oxygen plasma. 
 
     
     
       13. The method of  claim 9 , wherein depositing the first and second oxide layers comprises:
 depositing a layer of oxide material on the first and second fin structures; and 
 treating the deposited layer of oxide material with an oxygen plasma at an energy ranging from about 400 W to about 600 W. 
 
     
     
       14. The method of  claim 9 , wherein depositing the first and second gate electrodes comprises depositing first and second polysilicon structures. 
     
     
       15. The method of  claim 14 , further comprising:
 removing the first and second polysilicon structures; 
 depositing a photoresist layer on portions of the first oxide layer exposed by the removing the first polysilicon structure; 
 etching portions of the second oxide layer exposed by the removing the second polysilicon structure; 
 forming a first metal gate electrode on the portions of the first oxide layer; and 
 forming a second metal gate electrode on the portions of the second oxide layer. 
 
     
     
       16. A semiconductor device, comprising:
 a first fin field effect transistor (finFET) on a substrate, the first finFET comprising:
 a first fin structure on the substrate, and 
 a first gate structure comprising a first oxide layer on the first fin structure, a first thickness of a first portion of the first oxide layer on a top surface of the first fin structure being greater than a second thickness of a second portion of the first oxide layer on a sidewall of the first fin structure; and 
 
 a second finFET on the substrate, the second finFET comprising:
 a second fin structure on the substrate, and 
 a second gate structure comprising a second oxide layer on the second fin structure, a first thickness of a first portion of the second oxide layer on a top surface of the second fin structure being substantially equal to a second thickness of a second portion of the second oxide layer on a sidewall of the second fin structure. 
 
 
     
     
       17. The semiconductor device of  claim 16 , further comprising first and second layers of amorphous silicon on the top surfaces of the first and second fin structures. 
     
     
       18. The semiconductor device of  claim 16 , wherein the first thickness of the first portion of the first oxide layer is greater than the second thickness of the second portion of the first oxide layer by a value ranging from about 0.5 nm to about 3 nm. 
     
     
       19. The semiconductor device of  claim 16 , wherein the first gate structure further comprises:
 a dielectric layer on the first oxide layer; and 
 a gate electrode on the dielectric layer. 
 
     
     
       20. The semiconductor device of  claim 16 , further comprising spacers on sidewalls of the first gate structure, wherein the first oxide layer extends under the spacers.