OTP-MTP on FDSOI architecture and method for producing the same

Abstract

Methods of forming a compact FDSOI OTP/MTP cell and a compact FinFET OTP/MTP cell and the resulting devices are provided. Embodiments include forming a SOI region or a fin over a BOX layer over a substrate; forming a first and a second gate stack, laterally separated, over respective portions of the SOI region or the fin; forming a first and a second liner along each first and second sidewall and of the first and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; forming a spacer on each first and second liner; forming a S/D region in the SOI region or the fin between the first and the second gate stack; forming a CA over the S/D region; utilizing each gate of the first gate stack and the second gate stack as a WL; and connecting a BL to the CA.

What is claimed is: 
     
       1. A device comprising:
 a silicon-on-insulator (SOI) region or a fin over a buried oxide (BOX) layer over a substrate; 
 a first shallow trench isolation (STI) structure and a second STI structure through the BOX layer and a portion of the substrate on opposite sides of the SOI region; 
 a first gate stack and a second gate stack, laterally separated, over respective portions of the SOI region or the fin, the first gate stack and the second gate stack having:
 a first native oxide layer and a second native oxide layer, respectively; 
 a first oxide/high-k layer and a second oxide/high-k layer over the first native oxide layer and the second native oxide layer, respectively; 
 a first metal layer and a second metal layer over the first oxide/high-k layer and the second/high-k layer, respectively; 
 a first polysilicon gate layer and a second polysilicon gate layer over the first metal layer and the second metal layer, respectively; and 
 a first silicide layer and a second silicide layer over the first polysilicon gate layer and the second polysilicon gate layer, respectively; 
 
 a first liner and a second liner along each first sidewall and second sidewall of the first gate stack and the second gate stack, respectively, the second sidewall over respective portions of the SOI region or the fin; 
 a spacer on each first liner and second liner; 
 a source/drain (S/D) region in the SOI region or the fin between the first gate stack and the second gate stack; 
 an interlayer dielectric (ILD) layer over the substrate; 
 a source/drain contact (CA) through a portion of the ILD over the S/D region; and 
 a bit line (BL) connected to the CA, 
 wherein a portion of the first polysilicon gate extends over a portion of the first STI structure and a portion of the second first polysilicon gate extends over a portion of the first STI structure. 
 
     
     
       2. The device according to  claim 1 , wherein
 the first gate stack and a first liner are over a portion of the first STI structure and the second gate stack and a first liner are over a portion of the second STI structure. 
 
     
     
       3. The device according to  claim 2 , wherein
 the first native oxide layer and the second native oxide layer are disposed over the portion of the first STI structure and the portion of the second STI structure, respectively, and 
 the first silicide layer and the second silicide layer are coplanar with an upper surface of the first liner and the second liner. 
 
     
     
       4. The device according to  claim 1 , wherein the fin is formed, the device further comprising:
 the first gate stack and the second gate stack adjacent to a first sidewall and a second sidewall of the fin, respectively, the first sidewall and the second sidewall on opposite sides of the fin. 
 
     
     
       5. The device according to  claim 4 , wherein the first gate stack and the second gate stack each further comprise:
 a first native oxide layer and a second native oxide layer adjacent to the first sidewall and the second sidewall of the fin, respectively, and over respective portions of the fin; 
 the first oxide/high-k layer and the second oxide/high-k layer over and along the first native oxide layer and the second native oxide layer, respectively; 
 a first metal layer and a second metal layer over and along the first oxide/high-k layer and the second/high-k layer, respectively; 
 a first polysilicon gate layer and a second polysilicon gate layer over and along the first metal layer and the second metal layer, respectively; and 
 a first silicide layer and a second silicide layer over the first polysilicon gate layer and the second polysilicon gate layer, respectively, the first silicide layer and the second silicide layer coplanar with an upper surface of the first liner and the second liner. 
 
     
     
       6. The device according to  claim 1 , further comprising a raised source/drain (RSD) between the S/D region and the CA.