Semiconductor device assembly with heat transfer structure formed from semiconductor material

Abstract

Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

We claim: 
     
       1. A method of forming a semiconductor device assembly, comprising:
 forming a cavity in a substrate; 
 attaching a first semiconductor die to a recessed surface of the cavity; 
 stacking a second semiconductor die above the first semiconductor die, wherein the second semiconductor die is coupled with the first semiconductor die via a plurality of conductive elements; 
 disposing an underfill material in the cavity, wherein a portion of a sidewall of the cavity is exposed exclusive of the underfill material; and 
 attaching a third semiconductor die over the cavity. 
 
     
     
       2. The method of  claim 1 , wherein disposing the underfill material in the cavity includes:
 instilling the underfill material in interstitial space between the first semiconductor die and the second semiconductor die; and 
 accumulating an excess portion of the underfill material in a gap between the sidewall of the cavity and the stack of the first and second semiconductor dies. 
 
     
     
       3. The method of  claim 1 , wherein the second semiconductor die includes a plurality of through-silicon vias (TSVs) configured to couple bond pads of the first semiconductor die with bond pads of the third semiconductor die via the plurality of conductive elements. 
     
     
       4. The method of  claim 1 , wherein the third semiconductor die includes a base region and a peripheral region adjacent to the base region, and wherein attaching the third semiconductor die over the cavity comprises attaching the base region to the second semiconductor die and the peripheral region to two or more outer regions of the substrate that surround the cavity. 
     
     
       5. The method of  claim 4 , wherein the two or more outer regions each comprise a recessed portion and a raised portion peripheral to the recessed portion, and wherein attaching the third semiconductor die over the cavity comprises attaching a peripheral region of the third semiconductor die to the recessed portions of the two or more outer regions. 
     
     
       6. The method of  claim 5 , further comprising:
 attaching a support substrate to the raised portions of the two or more outer regions, wherein the support substrate is electrically coupled to the first, second, third semiconductor dies, or a combination thereof. 
 
     
     
       7. The method of  claim 6 , wherein the raised portion forms a ridge with respect to the recessed portion to secure the third semiconductor die between the support substrate and the substrate. 
     
     
       8. The method of  claim 1 , wherein the third semiconductor die comprises a portion over the cavity that is exposed exclusive of the underfill material. 
     
     
       9. A method of forming a semiconductor device assembly, comprising:
 forming a structure from a semiconductor substrate, the structure including an inner region, an outer region surrounding and projecting from the inner region, and a cavity defined by the inner region and the outer region; 
 selectively recessing a first portion of the outer region adjacent to a second portion of the outer region, wherein the first portion is immediately next to the cavity; 
 attaching a stack of first semiconductor dies to a recessed surface of the cavity; 
 disposing an underfill material in the cavity after attaching the stack of first semiconductor dies, wherein an excess portion of the underfill material forms a fillet in a gap between a sidewall of the cavity and the stack of first semiconductor dies; 
 attaching a second semiconductor die to the recessed first portion of the outer region, the second semiconductor enclosing the stack of first semiconductor dies within the cavity; and 
 attaching a support substrate to the second portion of the outer region. 
 
     
     
       10. The method of  claim 9 , wherein a sidewall of the cavity is in contact with an edge of the first semiconductor dies of the stack. 
     
     
       11. The method of  claim 9 , wherein attaching the second semiconductor die to the recessed first portion of the outer region comprises:
 attaching a base region of the second semiconductor die to the stack of first semiconductor dies; and 
 attaching a peripheral region of the second semiconductor die adjacent to the base region to the recessed first portion of the outer region. 
 
     
     
       12. The method of  claim 9 , wherein a peripheral region of the second semiconductor die includes a first circuit component having a greater power density than a second circuit component included in a base region of the second semiconductor die adjacent to the peripheral region. 
     
     
       13. The method of  claim 9 , wherein attaching the support substrate to the second portion of the outer region comprises:
 attaching the support substrate to the second semiconductor die such that the support substrate is electrically coupled to the stack of first semiconductor dies, the second semiconductor die, or both. 
 
     
     
       14. The method of  claim 9 , wherein the recessed first portion and the second portion of the outer region collectively form a support feature that secures the second semiconductor die between the support substrate and the structure. 
     
     
       15. The method of  claim 9 , wherein the second portion attached to the support substrate transfers heat between the support substrate and the outer region of the structure. 
     
     
       16. The method of  claim 9 , wherein:
 the second semiconductor die is attached to the recessed first portion of the outer region via a first adhesive material; and 
 the support substrate is attached to the second portion of the outer region via a second adhesive material. 
 
     
     
       17. A method of forming a semiconductor device assembly, comprising:
 forming a plurality of cavities in a semiconductor wafer, each cavity of the plurality including a recessed surface of the semiconductor wafer and a sidewall surface of the semiconductor wafer surrounding and extending from the recessed surface; 
 attaching a stack of first semiconductor dies to the recessed surface of each cavity, wherein the stack of first semiconductor dies is spaced apart from the sidewall surface by a gap; 
 disposing an underfill material in each cavity including the stack of first semiconductor dies, wherein an excess portion of the underfill material forms a fillet in the gap; 
 covering an opening of each cavity with a second semiconductor die that includes a base region and a peripheral region adjacent to the base region, wherein the peripheral region overlaps the opening by a first distance; and 
 singulating the semiconductor wafer using a plurality of dicing lanes, wherein each dicing lane of the plurality is spaced away from the opening of an adjacent cavity by a second distance that is greater than the first distance. 
 
     
     
       18. The method of  claim 17 , further comprising:
 attaching a support substrate to the second semiconductor die, wherein the support substrate is electrically coupled to the stack of first semiconductor dies, the second semiconductor die, or both. 
 
     
     
       19. The method of  claim 17 , wherein a distance between openings of the cavities is equal to or greater than a sum of a width of the dicing lane and twice of the first distance.