Fabrication of electrodes for memory cells

Abstract

Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a memory cell, thus decreasing the thickness variation. The subsequent layer fabricated may have a thickness variation that may be dependent on the thickness variation of the electrode layer. By decreasing the thickness variation of the electrode layer prior to forming the subsequent layer, the subsequent layer may also have a decreased thickness variation. The decreased thickness variation of the subsequent layer may impact the electrical behavior of memory cells formed from the subsequent layer. In some cases, the decreased thickness variation of the subsequent layer may allow for more predictable voltage thresholds for such memory cells, thus increasing the read windows for the memory cells.

What is claimed is: 
     
       1. A method, comprising:
 forming a first metal layer over an entire area of a die, wherein the first metal layer subsequently forms a plurality of access lines; 
 forming, above the first metal layer, a first electrode layer over the entire area of the die, wherein the first electrode layer is for a plurality of memory cells, wherein an upper surface of the first electrode layer has a first initial surface roughness, and wherein a first portion of the first electrode layer associated with a first memory cell of the plurality of memory cells has a first thickness after the forming and a second portion of the first electrode layer associated with a second memory cell of the plurality of memory cells has a second thickness after the forming that is different than the first thickness; 
 polishing the upper surface of the first electrode layer formed over the entire area of the die to change the upper surface from having the first initial surface roughness to having a first subsequent surface roughness that is less than the first initial surface roughness, wherein the first portion of the first electrode layer associated with the first memory cell has a third thickness after the polishing and the second portion of the first electrode layer associated with the second memory cell has a fourth thickness after the polishing, and wherein a second difference between the third thickness and the fourth thickness is less than a first difference between the first thickness and the second thickness; and 
 forming, after the polishing, a first active layer in contact with the upper surface of the first electrode layer, wherein a uniformity of a thickness of the first active layer is based at least in part on the first subsequent surface roughness. 
 
     
     
       2. The method of  claim 1 , wherein polishing the upper surface of the first electrode layer comprises:
 applying a chemical-mechanical planarization (CMP) process to the upper surface of the first electrode layer. 
 
     
     
       3. The method of  claim 1 , wherein:
 forming the first electrode layer comprises depositing an electrode material via a deposition process; and 
 polishing the upper surface of the first electrode layer comprises breaking a vacuum seal associated with the deposition process. 
 
     
     
       4. The method of  claim 1 , further comprising:
 forming a second electrode layer above the first active layer; and 
 forming a second active layer above the second electrode layer. 
 
     
     
       5. The method of  claim 4 , further comprising:
 polishing an upper surface of the second electrode layer before forming the second active layer to change the upper surface of the second electrode layer from having a second initial surface roughness to having a second subsequent surface roughness that is less than the second initial surface roughness. 
 
     
     
       6. The method of  claim 4 , further comprising:
 polishing an upper surface of the first active layer before forming the second electrode layer; or 
 polishing an upper surface of the second active layer. 
 
     
     
       7. The method of  claim 4 , wherein a storage component comprises at least a portion of the second active layer. 
     
     
       8. The method of  claim 4 , wherein:
 the first active layer comprises a first chalcogenide material; 
 the second active layer comprises a second chalcogenide material, wherein the second chalcogenide material is different from the first chalcogenide material; and 
 the first electrode layer and the second electrode layer each comprise carbon. 
 
     
     
       9. The method of  claim 4 , further comprising:
 forming a third electrode layer above the second active layer; 
 forming a second metal layer for a second access line, the second metal layer above the third electrode layer; and 
 polishing a surface of the third electrode layer prior to forming the second metal layer.