Forming FinFET with reduced variability

Abstract

A semiconductor structure is provided that includes active semiconductor fins that have a uniform fin channel height. The uniform fin channel height is achieved by forming semiconductor fins (active and sacrificial) on an entirety of semiconductor substrate thus there is no loading effect during a subsequently performed dielectric etch step which can lead to fin channel height variation and ultimately variation in device characteristics. A trench isolation structure is located adjacent to the active semiconductor fins. The trench isolation structure includes at least one dielectric plug having a second width and a dielectric pillar having a first width located on each side of the at least one dielectric plug. The second width of the at least one dielectric plug is less than the first width of each dielectric pillar, yet equal to a width of each semiconductor fin.

What is claimed is: 
     
       1. A semiconductor structure comprising:
 a plurality of semiconductor fins extending upward from a surface of a semiconductor substrate, wherein each semiconductor fin has a uniform channel height; 
 a trench isolation structure located adjacent to the plurality of semiconductor fins, wherein the trench isolation structure comprises at least one dielectric plug having a second width and a dielectric pillar having a first width located on each side of the at least one dielectric plug, wherein the second width of the at least one dielectric plug is less than the first width of each dielectric pillar, yet equal to a width of each semiconductor fin, and wherein the at least one dielectric plug has a topmost surface that is vertically offset and is located beneath a topmost surface of each dielectric pillar of the trench isolation structure; 
 a functional gate structure straddling a portion of each semiconductor fin; and 
 an interlayer dielectric material located laterally adjacent to the functional gate structure and above the trench isolation structure; wherein the interlayer dielectric material directly contacts the topmost surface of the at least one of the dielectric plug and an upper sidewall of the dielectric pillar. 
 
     
     
       2. The semiconductor structure of  claim 1 , further comprising additional dielectric pillars of the first width located between each neighboring pair of semiconductor fins. 
     
     
       3. The semiconductor structure of  claim 2 , wherein each dielectric pillar of the trench isolation structure and the additional dielectric pillars have a uniform height, and are composed of a first dielectric material. 
     
     
       4. The semiconductor structure of  claim 3 , wherein the at least one dielectric plug is composed of a second dielectric material that is compositionally different from the first dielectric material. 
     
     
       5. The semiconductor structure of  claim 4 , wherein the first dielectric material is composed of silicon dioxide, and the second dielectric material is composed of SiOCN. 
     
     
       6. The semiconductor structure of  claim 1 , wherein the at least one dielectric plug extends beneath a topmost surface of the semiconductor substrate. 
     
     
       7. The semiconductor structure of  claim 1 , wherein a first number of the semiconductor fins are present in a first device region, and a second number of semiconductor fins are present in a second device region, and wherein the first and second device regions are separated by the trench isolation structure.