Polysilicon structure including protective layer

Abstract

A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers.

What is claimed is: 
     
       1. A manufacture, comprising:
 a substrate comprising a first portion and a second portion; 
 a first polysilicon structure over the first portion of the substrate; 
 a second polysilicon structure over the second portion of the substrate; 
 two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion; and 
 a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing a sidewall of the two spacers above the concave corner region, and the protective layer covering an entirety of the lower portion of the spacers of the second polysilicon structure. 
 
     
     
       2. The manufacture of  claim 1 , wherein the two spacers are L-shaped spacers. 
     
     
       3. The manufacture of  claim 1 , further comprising:
 a static random access memory (SRAM) cell comprising the second polysilicon structure and the two spacers. 
 
     
     
       4. The manufacture of  claim 1 , further comprising:
 a one-time-programmable (OTP) device comprising the first polysilicon structure. 
 
     
     
       5. The manufacture of  claim 1 , wherein the protective layer comprises silicon oxide. 
     
     
       6. The manufacture of  claim 1 , further comprising another two spacers on opposite sidewalls of the first polysilicon structure. 
     
     
       7. The manufacture of  claim 6 , wherein the protective layer has a second maximum thickness over the another two spacers, and the second maximum thickness is equal to or less than 110% of a first maximum thickness of the protective layer over the first polysilicon structure. 
     
     
       8. The manufacture of  claim 1 , wherein the protective layer directly contacts the first portion of the substrate. 
     
     
       9. A semiconductor device, comprising:
 a substrate; 
 a first polysilicon structure over a first portion of the substrate; 
 a first spacer on a sidewall of the first polysilicon structure; 
 a second polysilicon structure over a second portion of the substrate; 
 a second spacer on a sidewall of the second polysilicon structure wherein the second spacer has a concave corner region between an upper portion and a lower portion; and 
 a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer at least partially exposes the upper portion of the second spacer, and the protective layer directly contacts the first portion and the second portion substrate. 
 
     
     
       10. The semiconductor device of  claim 9 , wherein a thickness of the protective layer over the concave corner region is at least 110% of a thickness of the protective layer over the first polysilicon structure. 
     
     
       11. The semiconductor device of  claim 9 , wherein a difference between a thickness of the protective layer over the concave corner region and a thickness of the protective layer over the first polysilicon structure is greater than 10% of the thickness of the protective layer over the first polysilicon structure. 
     
     
       12. The semiconductor device of  claim 9 , further comprising a static random access memory (SRAM) cell, wherein the second polysilicon structure is part of the SRAM cell. 
     
     
       13. The semiconductor device of  claim 9 , further comprising a one-time-programmable (OTP) device, wherein the first polysilicon structure is part of the OTP device. 
     
     
       14. The semiconductor device of  claim 9 , wherein the protective layer comprises silicon oxide.