Semiconductor device and method of forming the same

Abstract

A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a fin structure; 
 a gate electrode crossing over the fin structure; 
 a source-drain region in the fin structure aside the gate electrode; 
 a plug disposed over and electrically connected to the gate electrode; and 
 a hard mask structure, surrounding the plug and disposed over the gate electrode, wherein the hard mask structure comprises a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, a bottom surface of the second hard mask layer is substantially coplanar with a bottom surface of the plug, and a material of the first hard mask layer is different from a material of the second hard mask layer. 
 
     
     
       2. The semiconductor device as claimed in  claim 1 , wherein the material of the first hard mask layer comprises oxide, nitride or oxy-nitride. 
     
     
       3. The semiconductor device as claimed in  claim 1 , wherein the material of the first hard mask layer comprises SiN, and the material of the second hard mask layer comprises ZrO 2 . 
     
     
       4. The semiconductor device as claimed in  claim 1 , further comprising:
 a contact etch stop layer (CESL) aside the gate electrode; and 
 a spacer disposed between the gate electrode and the contact etch stop layer, wherein the hard mask structure covers a top surface of the contact etch stop layer and covers a top surface of the spacer. 
 
     
     
       5. The semiconductor device as claimed in  claim 4 , wherein the first hard mask layer partially covers the top surface of the spacer. 
     
     
       6. The semiconductor device as claimed in  claim 1 , wherein the second hard mask layer contacts the plug. 
     
     
       7. The semiconductor device as claimed in  claim 1 , further comprising a plurality of conductive patterns disposed over and electrically connected to the source-drain region, wherein the hard mask structure is between the conductive patterns. 
     
     
       8. A semiconductor device, comprising:
 a fin structure; 
 a gate structure crossing over the fin structure, wherein the gate structure comprises a gate electrode and a spacer located over sidewalls of the gate electrode; 
 a source-drain region in the fin structure aside the gate structure; 
 a plug disposed over and electrically connected to the gate structure; 
 a contact etch stop layer (CESL) aside the gate structure; and 
 a hard mask structure, surrounding the plug and covers the gate structure and the contact etch stop layer, wherein the hard mask structure comprises a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, a k constant of a material of the first hard mask layer is lower than a k constant of a material of the second hard mask layer, and the second hard mask layer contacts the plug and a top surface of the contact etch stop layer. 
 
     
     
       9. The semiconductor device as claimed in  claim 8 , further comprising a plurality of conductive patterns disposed over and electrically connected to the source-drain region, wherein the hard mask structure is between the conductive patterns. 
     
     
       10. The semiconductor device as claimed in  claim 9 , wherein top surfaces of the conductive patterns are substantially coplanar with a top surface of the second hard mask layer. 
     
     
       11. The semiconductor device as claimed in  claim 9 , wherein the hard mask structure is disposed between and insulates the plug and the conductive patterns. 
     
     
       12. The semiconductor device as claimed in  claim 8 , wherein the first hard mask layer partially covers the top surface of the spacer. 
     
     
       13. The semiconductor device as claimed in  claim 8 , further comprising a dielectric layer disposed between the gate structure and the first hard mask layer. 
     
     
       14. The semiconductor device as claimed in  claim 8 , further comprising a conductive layer disposed between the gate electrode and the plug. 
     
     
       15. A method of forming a semiconductor device, comprising:
 forming a gate electrode crossing over a fin structure, wherein a source-drain region is in the fin structure aside the gate electrode; 
 removing a portion of the gate electrode; 
 forming a hard mask structure over the gate electrode, wherein the hard mask structure comprises a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer; and 
 forming a plug over the gate electrode, wherein the hard mask structure surrounds the plug, and a bottom surface of the second hard mask layer is substantially coplanar with a bottom surface of the plug. 
 
     
     
       16. The method as claimed in  claim 15 , wherein a method of forming the hard mask structure comprises:
 forming a dielectric layer aside the gate electrode, wherein a top surface of the dielectric layer is higher than a top surface of the gate electrode; 
 forming a material layer over the gate electrode, wherein a top surface of the material layer is lower than the top surface of the dielectric layer; 
 removing the dielectric layer while partially removing the material layer to form the first hard mask layer and a hollow portion, wherein the hollow portion exposes a top surface and sidewalls of the first hard mask layer; and 
 forming the second hard mask layer in the hollow portion. 
 
     
     
       17. The method as claimed in  claim 16 , wherein an etch selectivity of the dielectric layer is different from an etch selectivity of the material layer. 
     
     
       18. The method as claimed in  claim 17 , wherein the portion of the gate electrode is removed to form a recess, and the dielectric layer is disposed on sidewalls of the recess. 
     
     
       19. The method as claimed in  claim 17 , wherein the dielectric layer is disposed on a sidewall of the gate structure and extended onto the source-drain region. 
     
     
       20. The method as claimed in  claim 19 , wherein after the dielectric layer and the material layer are partially removed, a modification process is performed to form the first hard mask layer with a k constant lower than a material of the second hard mask layer.