US11056457B2ActiveUtilityA1

Semiconductor device with bond wire reinforcement structure

75
Assignee: NXP USA INCPriority: Sep 28, 2018Filed: Sep 28, 2018Granted: Jul 6, 2021
Est. expirySep 28, 2038(~12.2 yrs left)· nominal 20-yr term from priority
H10W 90/00H10W 74/016H10W 72/90H10W 72/075H10W 70/457H10W 72/552H10W 72/5522H10W 74/00H10W 90/28H10W 72/884H10W 90/754H10W 72/877H10W 72/865H10W 72/551H10W 72/07555H10W 90/756H10W 72/01515H10W 72/073H10W 72/354H10W 90/724H10W 90/734H10W 90/732H10W 42/121H10W 90/811H10W 74/111H10W 74/114H10W 76/40H10W 72/581H10W 72/07553H10W 72/50H10W 72/01551H10W 72/015H10W 74/01H10W 72/851H10W 70/465H10W 95/00H01L 24/09H01L 21/565H01L 24/85H01L 23/49582H01L 25/0657H01L 24/73H10W 72/5525
75
PatentIndex Score
2
Cited by
13
References
15
Claims

Abstract

A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.

Claims

exact text as granted — not AI-modified
The invention claimed is: 
     
       1. A packaged semiconductor device, comprising:
 a substrate having a plurality of input/output (I/O) pads; 
 a semiconductor die having a top, active surface, and a bottom, passive surface, wherein the bottom surface of the die is attached to a top surface of the substrate; 
 a plurality of bond wires electrically connecting die bonding pads on the die active surface to respective ones of the substrate I/O pads; 
 a fibrous bond-wire reinforcement structure formed over the bond wires and in contact with the bond wires; and 
 a molding compound formed over the bond wires, the fibrous bond-wire reinforcement structure, the top surface of the die, and the top surface of the substrate; 
 wherein the fibrous bond-wire reinforcement structure comprises a woven mat formed with a non-electrically conductive material. 
 
     
     
       2. The packaged semiconductor device of  claim 1 , wherein the fibrous bond-wire reinforcement structure comprises a woven fiberglass mat. 
     
     
       3. The packaged semiconductor device of  claim 1 , wherein the fibrous bond-wire reinforcement structure comprises a cellulose nanofiber mat. 
     
     
       4. The packaged semiconductor device of  claim 1 , wherein the fibrous bond-wire reinforcement structure further comprises an epoxy resin formed over the bond wires. 
     
     
       5. The packaged semiconductor device of  claim 1 , wherein the fibrous bond-wire reinforcement structure is sized and shaped to fit over the bond wires. 
     
     
       6. The packaged semiconductor device of  claim 1 , wherein at least a portion of each of the substrate I/O pads is exposed from the molding compound to allow for external electrical connection to the semiconductor die. 
     
     
       7. The packaged semiconductor device of  claim 1 , wherein the substrate comprises a metal lead frame. 
     
     
       8. The packaged semiconductor device of  claim 1 , wherein the semiconductor die comprises at least two semiconductor dies electrically connected to the substrate with bond wires. 
     
     
       9. The packaged semiconductor device of  claim 8 , wherein one of the at least two dies is stacked on top of another of the at least two dies. 
     
     
       10. A packaged semiconductor device, comprising:
 a substrate having a plurality of input/output (I/O) pads; 
 a semiconductor die having a top, active surface, and a bottom, passive surface, wherein the bottom surface of the die is attached to a top surface of the substrate; 
 a plurality of bond wires electrically connecting die bonding pads on the die active surface to respective ones of the substrate I/O pads; 
 a fibrous bond-wire reinforcement structure formed over the bond wires and in contact with the bond wires; and 
 a molding compound formed over the bond wires, the fibrous bond-wire reinforcement structure, the top surface of the die, and the top surface of the substrate; 
 wherein the wherein the fibrous bond-wire reinforcement structure comprises cellulose nanofibers. 
 
     
     
       11. The packaged semiconductor device of  claim 10 , wherein at least a portion of each of the substrate I/O pads is exposed from the molding compound to allow for external electrical connection to the semiconductor die. 
     
     
       12. The packaged semiconductor device of  claim 10 , wherein the substrate comprises a metal lead frame. 
     
     
       13. The packaged semiconductor device of  claim 10 , wherein the semiconductor die comprises at least two semiconductor dies electrically connected to the substrate with bond wires. 
     
     
       14. The packaged semiconductor device of  claim 13 , wherein one of the at least two dies is stacked on top of another of the at least two dies. 
     
     
       15. The packaged semiconductor device of  claim 10 , wherein the fibrous bond-wire reinforcement structure is sized and shaped to fit over the bond wires.

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