Semiconductor structure and manufacturing method thereof

Abstract

A method for manufacturing a semiconductor structure includes forming a plurality of dummy semiconductor fins on a substrate. The dummy semiconductor fins are adjacent to each other and are grouped into a plurality of fin groups. The dummy semiconductor fins of the fin groups are recessed one group at a time.

What is claimed is: 
     
       1. A semiconductor structure comprising:
 a substrate; 
 a first active fin and a second active fin over the substrate; and 
 a plurality of dummy fins over the substrate and between the first active fin and the second active fin, wherein each of a first group of the plurality of dummy fins has a concave topmost surface, wherein each of a second group of the plurality of dummy fins has a convex topmost surface, and wherein no active fin is interposed between the first group of the plurality of dummy fins and the second group of the plurality of dummy fins. 
 
     
     
       2. The semiconductor structure of  claim 1 , further comprising an isolation region over the substrate and between the first active fin and the second active fin, the isolation region covering the plurality of dummy fins. 
     
     
       3. The semiconductor structure of  claim 2 , wherein a top surface of the first active fin and a top surface of the second active fin is above a top surface of the isolation region. 
     
     
       4. The semiconductor structure of  claim 1 , wherein a height of each of the plurality of dummy fins is less than a height of the first active fin and a height of the second active fin. 
     
     
       5. The semiconductor structure of  claim 1 , wherein the first group of the plurality of dummy fins is interposed between the first active fin and the second group of the plurality of dummy fins. 
     
     
       6. The semiconductor structure of  claim 1 , wherein the first group of the plurality of dummy fins comprises more dummy fins than the second group of the plurality of dummy fins. 
     
     
       7. The semiconductor structure of  claim 1 , wherein a first height of a first sidewall of a first dummy fin of the first group of the plurality of dummy fins is greater than a second height of a second sidewall of the first dummy fin of the first group of the plurality of dummy fins. 
     
     
       8. A semiconductor structure comprising:
 a substrate; 
 a first active fin over the substrate; and 
 a plurality of dummy fins over the substrate and adjacent the first active fin, wherein a triplet of the plurality of dummy fins have concave topmost surfaces, wherein a pair of the plurality of dummy fins have convex topmost surfaces, wherein the triplet of the plurality of dummy fins are interposed between the first active fin and the pair of the plurality of dummy fins, and wherein the plurality of dummy fins are shorter than the first active fin. 
 
     
     
       9. The semiconductor structure of  claim 8 , further comprising a second active fin, the plurality of dummy fins being interposed between the first active fin and the second active fin. 
     
     
       10. The semiconductor structure of  claim 9 , wherein the plurality of dummy fins are shorter than the second active fin. 
     
     
       11. The semiconductor structure of  claim 8 , further comprising an isolation region over the plurality of dummy fins. 
     
     
       12. The semiconductor structure of  claim 8 , wherein the plurality of dummy fins have a height variation of less than about 5 nm. 
     
     
       13. The semiconductor structure of  claim 8 , wherein the plurality of dummy fins have a height variation of less than about 2% of a height of the first active fin. 
     
     
       14. The semiconductor structure of  claim 8 , wherein a height of the first active fin is between about 100 nm to about 160 nm. 
     
     
       15. A semiconductor structure comprising:
 a substrate; 
 a first active fin and a second active fin over the substrate; 
 a plurality of dummy fins over the substrate and between the first active fin and the second active fin, wherein no active fin is interposed between each pair of adjacent dummy fins of the plurality of dummy fins, wherein a first dummy fin of the plurality of dummy fins has a first concave top surface, wherein a second dummy fin of the plurality of dummy fins has a second concave top surface, and wherein a third dummy fin of the plurality of dummy fins has a convex top surface; and 
 an isolation region over the substrate and between the first active fin and the second active fin, wherein the isolation region covers the plurality of dummy fins. 
 
     
     
       16. The semiconductor structure of  claim 15 , wherein the second dummy fin is interposed between the first dummy fin and the third dummy fin. 
     
     
       17. The semiconductor structure of  claim 15 , wherein a first height of a first sidewall of the first dummy fin is greater than a second height of a second sidewall of the first dummy fin. 
     
     
       18. The semiconductor structure of  claim 15 , wherein a height of the isolation region is less than a height of the first active fin and a height of the second active fin. 
     
     
       19. The semiconductor structure of  claim 15 , wherein the plurality of dummy fins have a height variation of less than about 2% of a height of the first active fin. 
     
     
       20. The semiconductor structure of  claim 15 , wherein a portion of the first active fin extends above a top surface of the isolation region.