Long channel and short channel vertical FET co-integration for vertical FET VTFET

Abstract

A semiconductor and a method of forming a semiconductor on a single chip, including forming a shallow trench isolation (STI) region on a short channel device and a long channel device, forming at least two vertical fins connected in the long channel device, and forming contacts on a source and drain regions for the long channel device and short channel device, wherein the contacts connect a top surface of the source or drain region for series FET (Field-Effect Transistor) connection for the long channel device.

What is claimed is: 
     
       1. A semiconductor chip, comprising:
 a short channel device comprising a first vertical FET (Field-Effect Transistor); 
 a long channel device comprising a second vertical FET integrated with a plurality of short channel devices; 
 a plurality of gates formed for the long channel device and a gate formed for the short channel device, 
 wherein the long channel device comprises a series connection of the plurality of short channel devices, 
 wherein the short channel device and the long channel device are co-integrated on a same chip, 
 wherein the long channel device comprises a plurality of series of fins that are bottom connected and integrated with each other while separating the plurality of gates; 
 a plurality of metal contacts connecting a top surface of source/drain regions for the plurality of series of fins in the long channel device; and 
 a second metal contact formed on a top source/drain region on the short channel device separate from the long channel device, and 
 wherein the gate of the short channel device and the plurality of gates of the long channel device have a same gate length. 
 
     
     
       2. The semiconductor chip according to  claim 1  being a monolithic chip, wherein long channel and short channel devices form vertically stacked field effect transistors (FET), and
 wherein the plurality of series of fins are parallel with each other, and 
 wherein the plurality of metal contacts connects at least two adjacent top surfaces of the source/drain regions and devoid of a contact with a top surface of a fin of the short channel device. 
 
     
     
       3. The semiconductor chip according  claim 1 , wherein the long channel device comprises the plurality of series of fins between spacers and gate regions,
 wherein the short channel device comprises a fin through the spacer and the gate regions, and 
 wherein the plurality of gates of the long channel device includes a common gate. 
 
     
     
       4. The semiconductor chip according  claim 1 , wherein the plurality of series of fins includes at least two vertical fins that are formed with bottom portions connected in the long channel device,
 wherein the plurality of series of fins of the long channel being connected with each other at a bottom portion of the plurality of series of fins while being separated from each other at a top portion of the plurality of series of fins, and 
 wherein the source/drain regions are formed over a top surface of the plurality of series of fins, and the plurality of metal contacts connecting the at least two vertical fins through the source/drain regions. 
 
     
     
       5. The semiconductor chip according  claim 1 ,
 wherein the plurality of metal contacts formed in the long channel device are electrically separate from the second metal contact in the short channel device, 
 wherein at least two adjacent top source or drain regions of the plurality of series of fins, which are not bottom connected by the bottom source or drain regions, are in electrical series connection by the metal contacts to provide a series connection for the long channel device, and 
 wherein the top source or drain region is in the short channel device. 
 
     
     
       6. The semiconductor chip according to  claim 1 , further comprising of:
 a single silicon substrate for both the long channel device and the short channel device; and 
 physically separate the gates formed on the substrate. 
 
     
     
       7. The semiconductor chip according to  claim 1 , further comprising of a well formed and defining a bottom source/drain regions for the short and long channel devices. 
     
     
       8. The semiconductor chip according to  claim 7 , further comprising a bottom spacer on the well for the short and long channel devices. 
     
     
       9. The semiconductor chip according to  claim 8 , wherein the gates formed is on the bottom spacer for the long and short channel devices. 
     
     
       10. The semiconductor chip according to  claim 9 , further comprising:
 a top spacer for the long and short channel devices; 
 the top source/drain regions formed on the top spacer. 
 
     
     
       11. The semiconductor chip according to  claim 1 , further comprising:
 the plurality of series of fins formed in the long channel device; and 
 the top source/drain regions formed on each of the plurality of series of fins above the top spacer. 
 
     
     
       12. The semiconductor chip according to  claim 1 ,
 wherein the long channel device comprises the series connection of the plurality of short channel devices with a common gate, 
 wherein a local interconnect connects at a top layer for the series connection of the plurality of short channel devices, 
 wherein the short channel device includes a fin, while the long channel device includes the plurality of series of fins, and 
 wherein the short channel device is electrically separate from the long channel device. 
 
     
     
       13. A semiconductor device, comprising:
 a short channel device being vertically formed; 
 a long channel device being vertically formed and co-integrated with the short channel device on a same chip; 
 a plurality of gates formed for the long channel device and a gate formed for the short channel device, 
 wherein the long channel device comprises:
 a well; 
 a plurality of vertical fins formed over the well; 
 source or drain regions formed over top surfaces of the plurality of vertical fins; and 
 a plurality of metal contacts connecting at least two of the plurality of vertical fins, 
 
 wherein the long channel device comprises a plurality of series of vertical fins that are bottom connected with each other while separating the plurality of gates; 
 a plurality of metal contacts connecting top surfaces of the source or drain regions for the series connection of the fins in the long channel device; and 
 a second metal contact formed on a top source or drain region on the short channel device separate from the long channel device, 
 wherein the gate of the short channel device and the plurality of gates of the long channel device have a same gate length. 
 
     
     
       14. The semiconductor device according to  claim 13 , further comprising a plurality of sets of gates formed on the same chip, each set of gates being physically separated by a dielectric material, and
 wherein the long channel device comprises a plurality of short channel devices forming a single transistor with a common gate, 
 wherein the short channel device includes a fin, while the long channel device includes the plurality of vertical fins, 
 wherein the plurality of metal contacts on the long channel device are separate from the second metal contact formed on the short channel device. 
 
     
     
       15. A semiconductor device on a single chip, the semiconductor comprising:
 a shallow trench isolation (STI) region formed for a short channel device and a long channel device in a substrate; 
 at least two vertical fins connected in the long channel device; 
 a plurality of gates formed for the long channel device and a gate formed for the short channel device, 
 wherein a plurality of metal contacts connect top surfaces of the source or drain regions for a series FET (Field-Effect Transistor) connection for the long channel device, 
 wherein the long channel device comprises a plurality of series of fins that are bottom connected with each other while separating the plurality of gates, 
 wherein the gate of the short channel device and the plurality of gates of the long channel device have a same gate length, 
 the plurality of metal contacts connecting the top surfaces of the source or drain regions for the series connection of the fins in the long channel device; and 
 a second metal contact formed on a top source or drain region on the short channel device. 
 
     
     
       16. The semiconductor device according to  claim 15 , further comprising:
 the plurality of gates physically separated by a dielectric material on the substrate, 
 wherein the substrate comprises a silicon substrate for the both the long channel device and the short channel device, and 
 wherein the long channel device comprises a plurality of short channel devices with a common gate. 
 
     
     
       17. The semiconductor device according to  claim 16 , wherein the at least two vertical fins are formed from the substrate by patterning, and
 wherein the plurality of metal contacts on the long channel device are separate from the second metal contact formed on the short channel device. 
 
     
     
       18. The semiconductor device according to  claim 17 , further comprising a well defining a bottom source or drain region for the short and long channel devices. 
     
     
       19. The semiconductor device according to  claim 18 , further comprising a bottom spacer connected to the well for the short and long channel devices. 
     
     
       20. The semiconductor device according to  claim 19 , wherein the plurality of gates are formed on the bottom spacer for the long and short channel devices; and further comprising:
 a top spacer formed for the long and short channel devices, 
 wherein the long channel device includes the plurality of series of fins that are bottom connected and integrated with each other.