Semiconductor device and method of fabricating the same

Abstract

A semiconductor device includes a semiconductor substrate, a gate stack, an air spacer, a first spacer, a second spacer, a sacrificial layer, and a contact plug. The gate stack is on the semiconductor substrate. The air spacer is around the gate stack. The first spacer is around the air spacer. The second spacer is on the air spacer and the first spacer. The sacrificial layer is on the gate stack, and an etching selectivity between the second spacer and the sacrificial layer is in a range from about 10 to about 30. The contact plug lands on the second spacer and the gate stack.

What is claimed is: 
     
       1. A method of fabricating a semiconductor device, comprising:
 forming an interlayer dielectric layer and a gate stack on a semiconductor substrate; 
 forming an air spacer and a first spacer surrounding a sidewall of the gate stack, wherein the first spacer is on a sidewall of the interlayer dielectric layer, and the air spacer is between the gate stack and the first spacer; 
 forming a second spacer on the first spacer and the air spacer, wherein the second spacer has a portion in contact with a sidewall of the first spacer; 
 forming a first contact hole landing on the second spacer and the gate stack, wherein a sidewall of the first contact hole is defined by the second spacer; and 
 filling the first contact hole with a conductive material. 
 
     
     
       2. The method of  claim 1 , wherein forming the air spacer and the first spacer surrounding the sidewall of the gate stack comprises:
 forming a low-k spacer and a first spacer surrounding the sidewall of the gate stack; 
 removing a top portion of the low-k spacer and a top portion of the first spacer, such that a top surface of the gate stack is coplanar with a top surface of the first spacer and a top surface of the low-k spacer; and 
 replacing the low-k spacer with the air spacer. 
 
     
     
       3. The method of  claim 1 , wherein forming the second spacer on the first spacer and the air spacer comprises:
 depositing a second spacer material on the gate stack, the first spacer, a space between the gate stack and the first spacer, and the interlayer dielectric layer, and on a sidewall of the interlayer dielectric layer, wherein a portion of the second spacer material is embedded into the space and in contact with a sidewall of the gate stack; and 
 removing portions of the second spacer material on the gate stack and the interlayer dielectric layer. 
 
     
     
       4. The method of  claim 1 , further comprising:
 forming a third spacer surrounding the sidewall of the gate stack, wherein the third spacer is between the air spacer and the gate stack, a portion of the second spacer is on the third spacer, and a portion of the second spacer is in contact with a sidewall of the third spacer. 
 
     
     
       5. The method of  claim 4 , wherein the sidewall of the first contact hole is further defined by the third spacer. 
     
     
       6. The method of  claim 4 , wherein forming the second spacer on the first spacer, the air spacer, and the third spacer comprises:
 depositing a second spacer material on the gate stack, the first spacer, the third spacer, a space between the first spacer and the third spacer, and the interlayer dielectric layer, and on a sidewall of the interlayer dielectric layer and a first sidewall of the third spacer, wherein a portion of the second spacer material is embedded into the space and in contact with a second sidewall of the third spacer; and 
 removing portions of the second spacer material on the gate stack and the interlayer dielectric layer, and on the first sidewall of the third spacer. 
 
     
     
       7. The method of  claim 4 , wherein forming the air spacer, the first spacer, and the third spacer surrounding the sidewall of the gate stack comprises:
 forming the first spacer, a low-k spacer, and the third spacer surrounding the sidewall of the gate stack, wherein the low-k spacer is between the first spacer and the third spacer; 
 removing a top portion of the first spacer, a top portion of the low-k spacer, and a top portion of the third spacer, such that a top surface of the first spacer, a top surface of the low-k spacer, and a top surface of the third spacer are higher than a top surface of the gate stack; and 
 replacing the low-k spacer with the air spacer. 
 
     
     
       8. The method of  claim 4 , further comprising:
 replacing the interlayer dielectric layer with a bottom conductive structure; 
 removing a top portion of the bottom conductive structure, such that a top surface of the bottom conductive structure is coplanar with a top surface of the gate stack; 
 forming a second contact hole landing on the second spacer and the bottom conductive structure, wherein a sidewall of the second contact hole is defined by the first spacer and the second spacer; and 
 filling the second contact hole with the conductive material. 
 
     
     
       9. A method of fabricating a semiconductor device, comprising:
 forming a first spacer and a second spacer on a sidewall of a dummy gate stack; 
 replacing the dummy gate stack with a gate structure; 
 etching back the gate structure; 
 after etching back the gate structure, removing the first spacer to form an air spacer between the etched gate structure and the second spacer; 
 forming a third spacer on the second spacer and the air spacer; and 
 forming a conductive contact on the etched gate structure and in contact with a sidewall of the third spacer. 
 
     
     
       10. The method of  claim 9 , further comprising forming a dielectric cap after forming the third spacer and prior to forming the conductive contact. 
     
     
       11. The method of  claim 10 , wherein forming the dielectric cap is such that a bottommost surface of the dielectric cap is higher than a bottommost surface of the third spacer. 
     
     
       12. The method of  claim 10 , wherein forming the dielectric cap is such that the dielectric cap is spaced apart from the air spacer. 
     
     
       13. The method of  claim 9 , wherein forming the third spacer comprises:
 forming a dielectric layer lining a sidewall of the second spacer and a top surface of the etched gate structure; and 
 removing a portion of the dielectric layer over the top surface of the etched gate structure. 
 
     
     
       14. The method of  claim 9 , wherein forming the conductive contact is such that the conductive contact is further in contact with a top surface of the third spacer. 
     
     
       15. A method of fabricating a semiconductor device, comprising:
 forming an interlayer dielectric layer and a gate stack on a semiconductor substrate; 
 forming an air spacer between the gate stack and the interlayer dielectric layer; 
 forming a first spacer to cover the air spacer and expose a top surface of the gate stack, wherein a bottom surface of the first spacer is lower than a top surface of the interlayer dielectric layer; 
 forming a dielectric cap over the gate stack, wherein a portion of the first spacer is between the dielectric cap and the interlayer dielectric layer; 
 after forming the dielectric cap, forming a recess in the dielectric cap such that the recess exposes a sidewall of the first spacer; and 
 forming a conductive contact in the recess of the dielectric cap to be electrically connected to the gate stack. 
 
     
     
       16. The method of  claim 15 , wherein forming the dielectric cap is such that a bottommost surface of the dielectric cap is lower than a bottommost surface of the first spacer. 
     
     
       17. The method of  claim 15 , wherein forming the interlayer dielectric layer and the gate stack comprises:
 forming a dummy gate over the semiconductor substrate; 
 forming a second spacer and a third spacer on a sidewall of the dummy gate; 
 forming the interlayer dielectric layer on a sidewall of the third spacer; and 
 replacing at least a portion of the dummy gate with the gate stack. 
 
     
     
       18. The method of  claim 17 , wherein forming the interlayer dielectric layer and the gate stack further comprises:
 forming a fourth spacer on the sidewall of the dummy gate such that the second spacer is between the fourth spacer and the third spacer. 
 
     
     
       19. The method of  claim 18 , wherein forming the air spacer comprises removing the second spacer and etching back the fourth spacer. 
     
     
       20. The method of  claim 17 , wherein forming the air spacer comprises removing the second spacer and etching back the third spacer.