Tunnel polarization junction III-N transistors

Abstract

Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.

What is claimed is: 
     
       1. A transistor structure comprising:
 a first layer comprising a first crystalline III-N material; 
 a second layer comprising a second crystalline III-N material; 
 an intervening layer other than a III-N material between the first layer and the second layer, wherein the first crystalline III-N material has a first crystal orientation and the second crystalline III-N material has a second crystal orientation inverted with respect to the first crystal orientation; and 
 a source, a drain, and a gate coupled to the first layer. 
 
     
     
       2. The transistor structure of  claim 1 , wherein the first and second crystalline III-N materials comprise gallium nitride. 
     
     
       3. The transistor structure of  claim 1 , wherein the first crystal orientation comprises a first c-axis out of plane with respect to the first layer, the second crystal orientation comprises a second c-axis out of plane with respect to the second layer, and the first c-axis and the second c-axis are substantially aligned. 
     
     
       4. The transistor structure of  claim 1 , wherein the first crystalline III-N material comprises a group III-face adjacent to the intervening layer and a nitrogen (N)-face opposite the intervening layer and the second crystalline III-N material comprises a group III-face adjacent to the intervening layer and a nitrogen (N)-face opposite the intervening layer. 
     
     
       5. The transistor structure of  claim 1 , wherein the first crystalline III-N material comprises a nitrogen (N)-face adjacent to the intervening layer and a group III-face opposite the intervening layer and the second crystalline III-N material comprises a nitrogen (N)-face adjacent to the intervening layer and a group III-face opposite the intervening layer. 
     
     
       6. The transistor structure of  claim 1 , wherein the intervening layer comprises a third crystalline material having a thickness of not more than 5 nm. 
     
     
       7. The transistor structure of  claim 6 , wherein the third crystalline material comprises oxygen and one or both of aluminum and scandium. 
     
     
       8. The transistor structure of  claim 1 , further comprising:
 a third layer on the intervening layer, wherein the third layer comprises a third crystalline III-N material having a different composition than the first crystalline III-N material and the third crystalline III-N material has a third crystal orientation that is inverted with respect to the second crystal orientation, wherein the first layer is on the third layer. 
 
     
     
       9. The transistor structure of  claim 1 , wherein the intervening layer comprises an amorphous material having a thickness of not more than 5 nm. 
     
     
       10. The transistor structure of  claim 9 , wherein the amorphous material comprises at least one of aluminum oxide, silicon oxide, silicon nitride, or silicon oxynitride. 
     
     
       11. The transistor structure of  claim 1 , wherein the first crystalline III-N material comprises gallium nitride having a gallium-face adjacent to the intervening layer and a nitrogen-face opposite the intervening layer, the second crystalline III-N material comprises gallium nitride having a gallium-face adjacent to the intervening layer and a nitrogen-face opposite the intervening layer, the intervening layer comprises a third crystalline material comprising oxygen and aluminum, and the source and the drain comprise n-doped indium gallium nitride. 
     
     
       12. A system comprising:
 a memory; and 
 an integrated circuit coupled to the memory, the integrated circuit including a transistor structure comprising:
 a first layer comprising a first crystalline III-N material; 
 a second layer comprising a second crystalline III-N material; 
 an intervening layer other than a III-N material between the first layer and the second layer, wherein the first crystalline III-N material has a first crystal orientation and the second crystalline III-N material has a second crystal orientation inverted with respect to the first crystal orientation; and 
 a source, a drain, and a gate coupled to the first layer. 
 
 
     
     
       13. The system of  claim 12 , wherein the transistor structure comprises a PMOS transistor structure and the integrated circuit further comprises:
 a substrate, wherein the first layer is on the substrate; and 
 an NMOS transistor structure comprising:
 a third layer on the substrate, the third layer comprising a third crystalline III-N material; 
 a polarization layer on the third layer; and 
 a second source, a second drain, and a second gate coupled to the third layer. 
 
 
     
     
       14. The system of  claim 12 , wherein the first crystalline III-N material comprises a group III-face adjacent to the intervening layer and a nitrogen (N)-face opposite the intervening layer and the second crystalline III-N material comprises a group III-face adjacent to the intervening layer and a nitrogen (N)-face opposite the intervening layer. 
     
     
       15. The system of  claim 13 , wherein the third crystalline III-N material comprises a group III-face adjacent to the polarization layer and a nitrogen (N)-face opposite the polarization layer. 
     
     
       16. The system of  claim 13 , wherein the first, second, and third crystalline III-N materials comprise gallium nitride and the source, the drain, the second source, and the second drain comprise n-doped indium gallium nitride. 
     
     
       17. The system of  claim 12 , wherein the intervening layer comprises a fourth crystalline material having a thickness of not more than 5 nm, the fourth crystalline material comprising oxygen and aluminum. 
     
     
       18. The system of  claim 12 , wherein the integrated circuit comprises one of a power management integrated circuit (PMIC) or a radio frequency integrated circuit (RFIC). 
     
     
       19. A method for fabricating a transistor structure comprising:
 forming a first layer comprising a first crystalline III-N material over a substrate; 
 disposing a second layer other than a III-N material over the first layer and a third layer comprising a second crystalline III-N material over the second layer, wherein the first crystalline III-N material has a first crystal orientation and the second crystalline III-N material has a second crystal orientation inverted with respect to the first crystal orientation; and 
 forming a source, a drain, and a gate coupled to the third layer. 
 
     
     
       20. The method of  claim 19 , wherein the second crystalline III-N material comprises a group III-face adjacent to the second layer and a nitrogen (N)-face opposite the second layer and the first crystalline III-N material comprises a group III-face adjacent to the second layer and a nitrogen (N)-face opposite the second layer.