US11302668B2ActiveUtilityA1

Multi-purpose non-linear semiconductor package assembly line

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Assignee: INFINEON TECHNOLOGIES AGPriority: Oct 4, 2016Filed: Dec 19, 2019Granted: Apr 12, 2022
Est. expiryOct 4, 2036(~10.2 yrs left)· nominal 20-yr term from priority
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Claims

Abstract

A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of producing packaged semiconductor devices, the method comprising:
 providing a first packaging substrate panel; 
 providing a second packaging substrate panel; and 
 moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism, 
 wherein first type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel, 
 wherein the control mechanism moves both of the first and second packaging substrate panels through the assembly line in a non-linear manner, 
 wherein the first type packaged semiconductor devices are formed by arranging a first semiconductor die on the first packaging substrate panel and encapsulating the first semiconductor die that is arranged on the first packaging substrate panel with an electrically insulating mold compound body, 
 wherein the second type packaged semiconductor devices are formed by arranging a second semiconductor die on the second packaging substrate panel and encapsulating the second semiconductor die that is arranged on the second packaging substrate panel with an electrically insulating mold compound body, and 
 wherein the first and second type packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration. 
 
     
     
       2. The method of  claim 1 , wherein the first and second type packaged semiconductor devices each comprise electrically conductive leads that are exposed from the mold compound body of the respective first and second type packaged semiconductor devices, and wherein the first and second packaged semiconductor devices differ with respect to a configuration of the electrically conductive leads relative to the mold compound body of the respective completed one of the first and second packaged semiconductor devices. 
     
     
       3. The method of  claim 1 , wherein the first type packaged semiconductor device is any one of: a transistor outline (TON) package type, a leadless package type, a Wafer Level Ball Grid Array (WLBGA) package type, and a flip chip package type, and wherein the second type packaged semiconductor device is any different one of: the transistor outline (TON) package type, the leadless package type, the Wafer Level Ball Grid Array (WLBGA) package type, and the flip chip package type. 
     
     
       4. The method of  claim 1 , wherein moving the first packaging substrate panel through the assembly line comprises:
 forming a second level metallization layer on a first metal layer of the first packaging substrate panel; and 
 structuring the second level metallization layer and the first metal layer to form a die pad and adjacent bond pads, the die pad and the bond pads being formed in both the first metal layer and the second level metallization layer. 
 
     
     
       5. The method of  claim 4 , wherein the first metal layer is a copper layer. 
     
     
       6. The method of  claim 4 , wherein the first type packaged semiconductor device is a quad flat no leads (QFN) package type. 
     
     
       7. The method of  claim 4 , wherein moving the first packaging substrate panel through the assembly line further comprises:
 attaching the first semiconductor die to the die pad; 
 forming electrical connections between the first semiconductor die and the bond pads; 
 encapsulating the first semiconductor die and the electrical connections by the electrically insulating mold compound of the first type packaged semiconductor device; and 
 removing portions of the first packaging substrate panel so as to expose the die pad and the bond pads. 
 
     
     
       8. The method of  claim 1 , wherein the control mechanism moves the first packaging substrate panel through a first subset of the package assembly tools and moves the second packaging substrate panel through a second subset of the package assembly tools, wherein the first subset of package assembly tools comprises at least one package assembly tool that is not in the second subset, and wherein the second subset of package assembly tools comprises at least one package assembly tool that is not in the first subset. 
     
     
       9. The method of  claim 1 , wherein the first and second packaging substrate panels are each at least 24″×18″. 
     
     
       10. A method of producing packaged semiconductor devices, the method comprising:
 providing first and second packaging substrate panels, each packaging substrate panel comprising a plurality of packaging sites; 
 providing an assembly line comprising a plurality of processing tools that are configured to perform package processing to each packaging site in the first and second packaging substrate panels; 
 providing a control mechanism that is configured to identify the first and second packaging substrate panels and to load the first and second packaging substrate panels into each one of the processing tools in the assembly line in a non-linear manner; 
 moving the first packaging substrate panel through the assembly line using the control mechanism to form first package type packages; and 
 moving the second packaging substrate panel through the assembly line using the control mechanism to form second package type packages that are different from the first package type packages, 
 wherein the control mechanism loads the first packaging substrate panels into only those processing tools in the assembly line that are required to produce the first package type packages and loads the second packaging substrate panels into only those processing tools in the assembly line that are required to produce the second package type packages, 
 wherein the processing tools in the assembly line that are required to produce the first package type packages are different from the processing tools in the assembly line that are required to produce the second package type packages, and 
 wherein the first and second package type packages differ with respect to at least one of: lead configuration, and encapsulant configuration, 
 wherein moving the first packaging substrate panel through the assembly line comprises:
 forming a second level metallization layer on a first metal layer of the first packaging substrate panel; 
 structuring the second level metallization layer and the first metal layer to form a die pad and adjacent bond pads, the die pad and the bond pads being formed in both the first metal layer and the second level metallization layer; 
 
 attaching a die to the die pad; 
 forming electrical connections between the die and the bond pads; 
 encapsulating the die and the electrical connections by an electrically insulating mold compound; and 
 removing portions of the first packaging substrate panel so as to expose the die pad and the bond pads.

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