Semiconductor device with isolation structure

Abstract

A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride liner is thicker than the first nitride liner.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a substrate with a first device area and a second device area; 
 first and second fin structures, wherein each of the first and second fin structures comprises a first fin portion disposed on the first device area and a second fin portion disposed on the second device area; 
 a first pair of gate structures disposed on the first fin portions of the first and second fin structures in the first device area; 
 a second pair of gate structures disposed on the second fin portions of the first and second fin structures in the second device area, wherein the second pair of gate structures is electrically isolated from the first pair of gate structures; 
 a first isolation structure interposed between the first pair of gate structures, wherein the first isolation structure comprises a first nitride liner and a first oxide fill layer; and 
 a second isolation structure interposed between the second pair of gate structures, wherein the second isolation structure comprises a second nitride liner and a second oxide fill layer and wherein the second nitride liner is thicker than the first nitride liner, and wherein the first and second isolation structures are substantially parallel to each other and to the first and second fin structures. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein first and second portions of the first and second isolation structures, respectively, are embedded in the substrate. 
     
     
       3. The semiconductor device of  claim 1 , wherein first and second portions of the first and second isolation structures, respectively, are embedded in a shallow trench isolation region disposed on the substrate. 
     
     
       4. The semiconductor device of  claim 1 , wherein the first isolation structure extends into the substrate by a first distance and the second isolation structure extends into the substrate by a second distance that is different from the first distance. 
     
     
       5. The semiconductor device of  claim 1 , wherein the first and second nitride liners comprise a silicon nitride material and the first and second oxide fill layers comprise a silicon oxide based material. 
     
     
       6. The semiconductor device of  claim 1 , wherein a dielectric constant of the first isolation structure is lower than a dielectric constant of the second isolation structure. 
     
     
       7. The semiconductor device of  claim 1 , wherein an average width of the first oxide fill layer is less than an average width of the second oxide fill layer. 
     
     
       8. The semiconductor device of  claim 1 , wherein an average width of the first isolation structure corresponds to a gate length of the first pair of gate structures and an average width of the second isolation structure corresponds to a gate length of the second pair of gate structures. 
     
     
       9. The semiconductor device of  claim 1 , wherein a gate pitch of the first pair of gate structures is smaller than a gate pitch of the second pair of gate structures. 
     
     
       10. The semiconductor device of  claim 1 , wherein an average width of the first isolation structure is less than an average width of the second isolation structure. 
     
     
       11. A semiconductor structure, comprising:
 a substrate with a memory device area and a logic device area; 
 fin structures with first fin portions disposed on the memory device area and second fin portions disposed on the logic device area; 
 a first pair of gate structures disposed on the first fin portions in the memory device area; 
 a second pair of gate structures disposed on the second fin portions in the logic device area, wherein the second pair of gate structures is electrically isolated from the first pair of gate structures; 
 a first isolation structure interposed between the first pair of gate structures, wherein the first isolation structure comprises a first pair of nitride liners, a first oxide liner interposed between the first pair of nitride liners, and a first oxide fill layer; and 
 a second isolation structure interposed between the second pair of gate structures, wherein the second isolation structure comprises a second pair of nitride liners, a second oxide liner interposed between the second pair of nitride liners, and a second oxide fill layer, and wherein the second oxide liner is thicker than the first oxide liner. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the second pair of nitride liners is thicker than the first pair of nitride liners. 
     
     
       13. The semiconductor device of  claim 11 , wherein the first oxide liner is thicker than each nitride liner of the first pair of nitride liners. 
     
     
       14. The semiconductor device of  claim 11 , wherein first and second portions of the first and second isolation structures, respectively, are embedded in the substrate. 
     
     
       15. The semiconductor device of  claim 11 , wherein a dielectric constant of the first isolation structure is lower than a dielectric constant of the second isolation structure. 
     
     
       16. A method, comprising:
 forming first and second gate structures on first and second fin structures disposed on a substrate; 
 forming first and second isolation trenches across the first and second gate structures, respectively, 
 wherein the first and second isolation trenches are substantially parallel to the first and second fin structures, 
 wherein the first isolation trench divides the first gate structure into a first pair of gate structures electrically isolated from each other and the second isolation structure divides the second gate structure into a second pair of gate structures electrically isolated from each other, and 
 wherein the forming the first and second isolation trenches comprises forming the first isolation trench to extend a first distance into the substrate and forming the second isolation trench to extend a second distance into the substrate, wherein the second distance is substantially equal to the first distance; and 
 forming first and second isolation structures within the first and second isolation trenches, respectively, wherein the forming the first and second isolation structures comprises forming the first isolation structure with a first dielectric constant and forming the second isolation structure with a second dielectric constant higher than the first dielectric constant. 
 
     
     
       17. The method of  claim 16 , wherein the forming the first and second isolation structures comprises depositing a nitride liner within the first and second isolation trenches, wherein a first portion of the nitride liner is deposited at a first deposition rate within the first isolation trench and a second portion of the nitride liner is deposited at a second deposition rate within the second isolation trench, and wherein the second deposition rate is faster than that the first deposition rate. 
     
     
       18. The method of  claim 16 , wherein the forming the first and second isolation structures comprises depositing a nitride liner within the first and second isolation trenches, wherein a first portion of the nitride liner is deposited with a first thickness within the first isolation trench and a second portion of the nitride liner is deposited with a second thickness within the second isolation trench, and wherein the second thickness is greater than the first thickness. 
     
     
       19. The method of  claim 16 , wherein the forming the first and second isolation structures comprises:
 depositing a nitride liner within the first and second isolation trenches; and 
 depositing an oxide fill layer on the nitride liner. 
 
     
     
       20. The method of  claim 16 , wherein the forming the first and second isolation structures comprises:
 depositing a first nitride liner within the first and second isolation trenches; 
 depositing an oxide liner on the first nitride liner; 
 depositing a second nitride liner on the oxide liner; and 
 
       depositing an oxide fill layer on the second nitride liner.