Semiconductor test device and manufacturing method thereof

Abstract

A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.

What is claimed is: 
     
       1. A semiconductor test device, the device comprising:
 first fin structures and second fin structures formed adjacent to the first fin structures, upper portions of the first and second fin structures protruding from an isolation insulating layer disposed over a substrate; 
 one or more dielectric layers formed over the first and second fin structures; 
 epitaxial layers formed to wrap the upper portions of the first and second fin structures; 
 silicide layers formed over the epitaxial layers; 
 a first contact layer contacting the silicide layer formed over a first point of the first fin structures, a second contact layer contacting the silicide layer over a second point of the first fin structures, and a third contact layer contacting the silicide layer at a third point of the second fin structures; and 
 a first pad coupled to the first contact layer via a first wiring, a second pad coupled to the second contact layer via a second wiring, and a third pad coupled to the third contact layer via a third wiring, 
 wherein the first to third contact layers are in contact with the isolation insulating layer without any portion of the one or more dielectric layers interposed between the first to third contact layers and the isolation insulating layer. 
 
     
     
       2. The device of  claim 1 , wherein the silicide layers fully cover a top and sides of the epitaxial layers, respectively. 
     
     
       3. The device of  claim 2 , wherein the silicide layers are in contact with the isolation insulating layer. 
     
     
       4. The device of  claim 2 , wherein:
 in the one or more dielectric layers, a first opening is disposed over the first point to expose the upper portions of the first fin structures, a second opening is disposed over the second point to expose the upper portions of the first fin structures, and a third opening is disposed over the third point to expose the upper portions of the second fin structures, and 
 the epitaxial layers are formed on the exposed upper portions of the first and second fin structures in the first to third openings. 
 
     
     
       5. The device of  claim 4 , wherein a number of the first fin structures exposed in the first and second openings is at least 10. 
     
     
       6. The device of  claim 5 , wherein a number of the second fin structures exposed in the third opening is at least 10. 
     
     
       7. The device of  claim 1 , wherein:
 the one or more dielectric layer comprises: 
 a first dielectric layer formed over the upper portions of the first and second fin structures; 
 a second dielectric layer formed over the first dielectric layer, and 
 the second dielectric layer is formed in a space between adjacent fin structures. 
 
     
     
       8. The device of  claim 2 , wherein the upper portions of the first and second fin structures include multiple layers of different semiconductor materials. 
     
     
       9. A semiconductor test device, the device comprising:
 first fin structures and second fin structures formed adjacent to the first fin structures, wherein each of the first fin structures and the second fin structures includes two or more first semiconductor layers and two or more second semiconductor layers alternately stacked and disposed over a bottom fin structure, 
 an isolation insulating layer formed such that upper portions of the first and second fin structures protrude from the isolation insulating layer; 
 one or more dielectric layers formed over the first and second fin structures; 
 in the one or more dielectric layers, a first opening is disposed over the upper portions of the first fin structures, a second opening is disposed over the upper portions of the first fin structures, and a third opening is disposed over the upper portions of the second fin structures; 
 epitaxial layers formed to wrap the upper portions of the first and second fin structures in the first, second and third openings; 
 silicide layers formed over the epitaxial layers; 
 a first contact layer contacting the silicide layer formed over a first point of the first fin structures, a second contact layer contacting the silicide layer over a second point of the first fin structures, and a third contact layer contacting the silicide layer at a third point of the second fin structures; and 
 a first pad coupled to the first contact layer via a first wiring, a second pad coupled to the second contact layer via a second wiring, and a third pad coupled to the third contact layer via a third wiring, 
 wherein the first to third contact layers are in contact with the isolation insulating layer without any portion of the one or more dielectric layers interposed between the first to third contact layers and the isolation insulating layer. 
 
     
     
       10. The device of  claim 9 , wherein the silicide layers fully cover a top and sides of the epitaxial layers, respectively, and are in contact with the isolation insulating layer. 
     
     
       11. The device of  claim 10 , wherein
 the epitaxial layers are formed on the exposed upper portions of the first and second fin structures in the first to third openings. 
 
     
     
       12. The device of  claim 11 , wherein the epitaxial layers formed to wrap an upper portion of the bottom fin structure. 
     
     
       13. The device of  claim 9 , wherein a number of the first fin structures exposed in the first and second openings is at least 10, and a number of the second fin structures exposed in the third opening is at least 10. 
     
     
       14. The device of  claim 9 , wherein a top of the bottom fin structure is located above an upper surface of the isolation insulating layer. 
     
     
       15. The device of  claim 9 , wherein the first semiconductor layers are made of Si and the second semiconductor layers are made of SiGe. 
     
     
       16. A semiconductor test device, the test device comprising:
 first fin structures and second fin structures formed adjacent to the first fin structures, upper portions of the first and second fin structures protruding from an isolation insulating layer disposed over a substrate; 
 one or more dielectric layers formed over the first and second fin structures; 
 in the one or more dielectric layers, a first opening formed over a first point of the first fin structures to expose the upper portions of the first fin structures, a second opening over a second point of the first fin structures to expose the upper portions of the first fin structures, and a third opening over a third point of the second fin structures to expose the upper portions of the second fin structures; 
 epitaxial layers formed to wrap the upper portions of the first and second fin structures in the first, second and third openings, respectively; 
 silicide layers formed over the epitaxial layers; 
 a first contact layer contacting the silicide layer formed over the first fin structures in the first opening, a second contact layer contacting the silicide layer over the first fin structures in the second opening, and a third contact layer contacting the silicide layer in the third opening; and 
 a first pad coupled to the first contact layer via a first wiring, a second pad coupled to the second contact layer via a second wiring, and a third pad coupled to the third contact layer via a third wiring, 
 wherein the first fin structures include a left-most fin structure and a right-most fin structure, and 
 wherein a dielectric layer disposed on the isolation insulating layer is in direct contact with a top of upper portions of the left-most fin structure and the right-most fin structure. 
 
     
     
       17. The device of  claim 16 , wherein the silicide layers fully cover a top and sides of the epitaxial layers, respectively, and are in contact with the isolation insulating layer. 
     
     
       18. The device of  claim 17 , wherein:
 the one or more dielectric layer comprises:
 a first dielectric layer formed over the upper portions of the first and second fin structures; 
 a second dielectric layer formed over the first dielectric layer, and 
 
 the second dielectric layer formed is in a space between adjacent fin structures. 
 
     
     
       19. The device of  claim 18 , wherein:
 the silicide layer comprises one of WSi, CoSi, NiSi, TiSi, MoSi or TaSi. 
 
     
     
       20. The device of  claim 16 , wherein each of the first fin structures and the second fin structures includes two or more first semiconductor layers and two or more second semiconductor layers alternately stacked.