Metal gate modulation to improve kink effect

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view.

What is claimed is: 
     
       1. An integrated chip, comprising:
 a source region and a drain region disposed within an upper surface of a substrate; 
 one or more dielectric materials disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region, wherein the one or more dielectric materials comprise one or more interior surfaces defining a recess within the one or more dielectric materials; and 
 a gate structure disposed over the substrate between the source region and the drain region, wherein the gate structure comprises a first gate material over the upper surface of the substrate and a second gate material, the second gate material completely filling the recess as viewed along a cross-sectional view. 
 
     
     
       2. The integrated chip of  claim 1 , wherein the second gate material has a greater maximum height than the first gate material. 
     
     
       3. The integrated chip of  claim 1 , wherein the second gate material has a protrusion extending outward from a lower surface of the second gate material. 
     
     
       4. The integrated chip of  claim 3 , wherein the lower surface of the second gate material is disposed directly over the upper surface of the substrate. 
     
     
       5. The integrated chip of  claim 1 ,
 wherein the second gate material has a first segment arranged over a first edge of the one or more dielectric materials and a second segment arranged over a second edge of the one or more dielectric materials; and 
 wherein the first segment is completely separated from the second segment by the first gate material. 
 
     
     
       6. The integrated chip of  claim 1 , further comprising:
 a gate dielectric disposed on the upper surface of the substrate, wherein the second gate material continuously extends along an upper surface and a sidewall of the gate dielectric. 
 
     
     
       7. The integrated chip of  claim 1 , wherein the first gate material does not laterally overlap the second gate material. 
     
     
       8. The integrated chip of  claim 1 , further comprising:
 a contact etch stop disposed along sidewalls of the gate structure, wherein the contact etch stop is arranged within the recess along a second cross-sectional view taken along a different direction than the cross-sectional view. 
 
     
     
       9. The integrated chip of  claim 1 , wherein the first gate material is completely outside of the recess as viewed along the cross-sectional view. 
     
     
       10. The integrated chip of  claim 1 , wherein the second gate material has a maximum width along a topmost surface of the second gate material. 
     
     
       11. The integrated chip of  claim 1 , wherein a topmost surface of the second gate material extends past an outermost edge of the recess. 
     
     
       12. An integrated chip, comprising:
 a source region disposed within a substrate; 
 a drain region disposed within the substrate and separated from the source region along a first direction by a channel region; 
 a gate structure disposed over the substrate between the source region and the drain region, wherein the gate structure comprises:
 a first gate electrode region having a first work function; and 
 a second gate electrode region having a second work function that is different than the first work function; and 
 
 wherein the second gate electrode region has a first segment over a first edge of the channel region and a separate, second segment over an opposing second edge of the channel region, the channel region extending past opposing sides of the first segment and the second segment in the first direction. 
 
     
     
       13. The integrated chip of  claim 12 , wherein the first gate electrode region comprises a first gate material and the second gate electrode region comprises a second gate material that is different than the first gate material. 
     
     
       14. The integrated chip of  claim 13 ,
 wherein the first gate material has a greater width than the second gate material; and 
 wherein the first gate material has a smaller height than the second gate material. 
 
     
     
       15. The integrated chip of  claim 13 , further comprising:
 a gate dielectric contacting lower surfaces of both the first gate material and the second gate material. 
 
     
     
       16. The integrated chip of  claim 13 , wherein a top of the second gate material is wider than a bottom of the second gate material, the bottom of the second gate material being closer to the substrate than the top. 
     
     
       17. An integrated chip, comprising:
 a source region and a drain region comprising doped regions disposed within a substrate, wherein the substrate comprises sidewalls defining a trench that continuously extends in a closed path surrounding the source region and the drain region; 
 an isolation structure comprising one or more dielectric materials disposed within the trench, wherein the one or more dielectric materials have one or more surfaces defining a recess within an upper surface of the isolation structure; 
 a gate dielectric disposed on an upper surface of the substrate; 
 a gate structure disposed over the substrate between the source region and the drain region, the gate structure comprising a first gate material vertically extending completely through the gate structure and a second gate material vertically extending completely through the gate structure, wherein the first gate material continuously wraps around the second gate material along a closed and unbroken path; 
 one or more sidewall spacers arranged along outer sidewalls of the gate structure; 
 an etch stop layer disposed over the substrate and along outer sidewalls of the one or more sidewall spacers; 
 a dielectric structure disposed over the etch stop layer and the gate structure; and 
 one or more conductive contacts extending through the dielectric structure to contact the gate structure. 
 
     
     
       18. The integrated chip of  claim 17 , wherein a topmost surface of the second gate material extends past an outer edge of the one or more dielectric materials. 
     
     
       19. The integrated chip of  claim 17 , wherein the etch stop layer, the first gate material, and the second gate material have upper surfaces that are substantially co-planar. 
     
     
       20. The integrated chip of  claim 17 , wherein the one or more conductive contacts are disposed on an upper surface of the first gate material.