Methods of cutting metal gates and structures formed thereof

Abstract

A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

What is claimed is: 
     
       1. A method comprising:
 forming an inter-layer dielectric; 
 forming a gate stack in the inter-layer dielectric; 
 selectively depositing a metal layer on the gate stack; 
 forming an inhibitor film on the metal layer, with at least a portion of the inter-layer dielectric being exposed through the inhibitor film; 
 selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon; and 
 etching to remove a portion of the gate stack to form an opening in the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask. 
 
     
     
       2. The method of  claim 1  further comprising, before the forming the inhibitor film, recessing the gate stack to form a recess, with the metal layer deposited in the recess. 
     
     
       3. The method of  claim 1 , wherein the forming the inhibitor film comprises selectively depositing a polymer film over the gate stack and outside of regions directly over the inter-layer dielectric. 
     
     
       4. The method of  claim 3 , wherein the depositing the polymer film comprises depositing polymerized fluorocarbon. 
     
     
       5. The method of  claim 1 , wherein the forming the inhibitor film is performed using a precursor comprising fluorocarbon. 
     
     
       6. The method of  claim 1 , wherein the selectively depositing the metal layer comprises atomic layer deposition. 
     
     
       7. The method of  claim 1  further comprising:
 filling a dielectric material into the opening to form an isolation region. 
 
     
     
       8. The method of  claim 7  further comprising:
 after the opening is filled, performing a planarization process on the dielectric material, with the dielectric hard mask being fully removed by the planarization process. 
 
     
     
       9. The method of  claim 1  further comprising:
 after the etching, filling a dielectric material into the opening; 
 after the dielectric material is filled, performing a planarization process on the dielectric material; and 
 forming a contact plug over and electrically coupling to the gate stack, wherein at a time after the contact plug is formed, a portion of the dielectric hard mask remains. 
 
     
     
       10. The method of  claim 9 , wherein the contact plug is over and contacting the metal layer. 
     
     
       11. The method of  claim 1 , wherein after the etching, an upper portion of a part of the dielectric hard mask is removed, and a lower portion of the part of the dielectric hard mask remains. 
     
     
       12. A method comprising:
 forming a dummy gate stack on a top surface and sidewalls of a semiconductor fin; 
 forming a source/drain region based on a part of the semiconductor fin; 
 forming a contact etch stop layer and an inter-layer dielectric, wherein the contact etch stop layer and the inter-layer dielectric cover the source/drain region; 
 replacing the dummy gate stack with a replacement gate stack, wherein the replacement gate stack comprises a high-k dielectric layer and a gate electrode on the high-k dielectric layer; 
 selectively depositing a metal layer covering the gate electrode; 
 selectively depositing a dielectric hard mask, wherein the dielectric hard mask comprises portions on opposing sides of the metal layer; 
 performing an etching process to remove a part of the replacement gate stack; and 
 after the etching process, removing the metal layer. 
 
     
     
       13. The method of  claim 12 , wherein the dielectric hard mask is prohibited from being deposited on the metal layer. 
     
     
       14. The method of  claim 12  further comprising forming an inhibitor film on the metal layer, wherein the dielectric hard mask is prohibited from being deposited on the metal layer by the inhibitor film. 
     
     
       15. The method of  claim 12  further comprising:
 filling a dielectric material into an opening left by the part of the replacement gate stack that has been removed; and 
 performing a planarization process on the dielectric material, wherein the metal layer is removed by the planarization process. 
 
     
     
       16. The method of  claim 12 , wherein the selectively depositing the metal layer is performed using atomic layer deposition. 
     
     
       17. A method comprising:
 forming an inter-layer dielectric having opposing portions, wherein the inter-layer dielectric comprises a first top surface; 
 forming a gate stack between the opposing portions of the inter-layer dielectric, wherein the gate stack comprises a second top surface; 
 selectively depositing a metal layer on the second top surface and away from the first top surface; 
 depositing an inhibitor film on the metal layer, wherein the inhibitor film is grown away from the first top surface; 
 selectively depositing a dielectric hard mask on the first top surface, with the inhibitor film being exposed during and after the dielectric hard mask is deposited; and 
 etching to remove a portion of the gate stack, wherein during and after the etching, the dielectric hard mask is used as a part of a respective etching mask. 
 
     
     
       18. The method of  claim 17  further comprising, after the dielectric hard mask is deposited, removing the inhibitor film. 
     
     
       19. The method of  claim 17 , wherein the inhibitor film further extends onto a third top surface of a gate spacer, and wherein the gate spacer is on a sidewall of the gate stack. 
     
     
       20. The method of  claim 17 , wherein the inhibitor film further extends onto a top edge of a contact etch stop layer, wherein the contact etch stop layer is between the gate stack and the inter-layer dielectric.