Three dimensional MIM capacitor having a comb structure and methods of making the same

Abstract

Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

What is claimed is: 
     
       1. A metal-insulator-metal (MIM) capacitor comprising:
 a first metal layer; 
 a second metal layer; 
 a dielectric layer located between the second metal layer and the first metal layer; 
 a first contact via structure electrically connected to the second metal layer and comprising a first top surface above the MIM capacitor; 
 a second contact via electrically connected to a metal line located below the MIM capacitor and comprising a second top surface above the MIM capacitor; and 
 a first etch stop layer and a second etch stop layer, wherein the second etch stop layer is located at greater distance from a substrate than the first etch stop layer, 
 wherein the first metal layer, the second metal layer and the dielectric layer are formed in a comb structure, wherein the comb structure comprises:
 a first tine structure of a first length; and 
 at least one second tine structure of a second length, wherein the first length is longer than the second length, and 
 
 wherein the first tine structure of the comb structure extends to the first etch stop layer and the at least one second tine structure of the comb structure extends to the second etch stop layer. 
 
     
     
       2. The capacitor of  claim 1 , wherein the second length is at least 0.25 times the first length. 
     
     
       3. The capacitor of  claim 1 , wherein the second etch stop layer comprises a secondary etch stop layer located directly on the first etch stop layer and the at least one second tine structure extends into the second etch stop layer. 
     
     
       4. The capacitor of  claim 1 , wherein the second length is at least 0.5 times the first length. 
     
     
       5. The capacitor of  claim 4 , wherein the first tine includes a stair step profile. 
     
     
       6. The capacitor of  claim 1 , further comprising:
 a second dielectric layer formed over the second metal layer; 
 a first blocking layer formed over the second dielectric layer; 
 a third dielectric layer formed over the first blocking layer; and 
 a second blocking layer formed over the third dielectric layer. 
 
     
     
       7. An integrated semiconductor device comprising:
 a first region comprising a plurality of metal-insulator-metal (MIM) capacitors, the MIM capacitors comprising:
 a first metal layer; 
 a second metal layer; 
 a dielectric layer located between the second metal layer and the first metal layer; 
 a first contact via structure electrically connected to the second metal layer and comprising a first top surface above the MIM capacitor; 
 a second contact via electrically connected to a metal line located below the MIM capacitor and comprising a second top surface above the MIM capacitor; and 
 a first etch stop layer and a second etch stop layer, wherein the second etch stop layer is located at greater distance from a substrate than the first etch stop layer, 
 wherein the first metal layer, the second metal layer and the dielectric layer are formed in a comb structure, wherein the comb structure comprises a first tine structure and at least one second tine structure, and 
 wherein a first tine of the comb structure extends to the first etch stop layer and the at least one second tine structure of the comb structure extends to the second etch stop layer; and 
 
 a second region comprising logic circuits. 
 
     
     
       8. The integrated semiconductor device of  claim 7 , wherein the integrated semiconductor device may be formed in a back-end-of-line (BEOL) portion over a metal line embedded within an interlayer dielectric level (IDL) layer. 
     
     
       9. The integrated semiconductor device of  claim 8 , wherein the integrated semiconductor device is a CIS global shutter. 
     
     
       10. The integrated semiconductor device of  claim 7 , further comprising an interposer. 
     
     
       11. A method of making a metal-insulator-metal (MIM) capacitor comprising:
 providing a dielectric layer; 
 forming a first trench in the dielectric layer; 
 forming one or more second trenches in the dielectric layer; 
 conformally depositing a first metal layer on sidewalls and a bottom surface of the first trench and the one or more second trenches; 
 conformally depositing a first high k dielectric layer over the first metal layer on the sidewalls and the bottom surface of the first trench and the one or more second trenches; 
 depositing a second metal layer in the first trench and the one or more second trenches over the first high k dielectric layer; 
 depositing a second dielectric layer over the second metal layer, a first blocking layer over the second dielectric layer, a third dielectric layer over the first blocking layer, and a second blocking layer over the third dielectric layer; 
 forming a first contact via structure that is electrically connected to the second metal layer and comprising a first top surface above the MIM capacitor; and 
 forming a second contact via that is electrically connected to a metal line located below the MIM capacitor and comprising a second top surface above the MIM capacitor, 
 wherein the first metal layer, the first high k dielectric layer and the second metal layer are formed in a comb structure, wherein the comb structure comprises a first tine structure formed in the first trench and at least one second tine structure formed in the one or more second trenches. 
 
     
     
       12. The method of  claim 11 , further comprising conformally depositing at least one metal barrier layer on sidewalls and a bottom surface of the first trench and the one or more second trenches prior to conformally depositing the first high k dielectric layer. 
     
     
       13. The method of  claim 11 , further comprising:
 patterning the second blocking layer, the third dielectric layer, the first blocking layer and the second dielectric layer; 
 depositing an oxide layer over the patterned second blocking layer, the patterned third dielectric layer, the patterned first blocking layer and the patterned second dielectric layer; 
 planarizing the oxide layer; and 
 forming a contact via structure to the MIM capacitor. 
 
     
     
       14. The method of  claim 11 , wherein providing an dielectric layer comprises:
 forming a first etch stop layer; 
 forming a first dielectric layer over the first etch stop layer; 
 forming a second etch stop layer over the first dielectric layer; 
 forming a second dielectric layer over the second etch stop layer; and 
 forming a third dielectric layer over the second etch stop layer. 
 
     
     
       15. The method of  claim 14 , wherein forming the one or more second trenches in the dielectric layer; comprises etching through the third dielectric layer and stopping at the second etch stop layer. 
     
     
       16. The method of  claim 11 , wherein providing a dielectric layer comprises:
 forming a first etch stop layer; 
 forming a second etch stop layer over the first etch stop layer, the second etch stop layer comprising a different material from the first etch stop layer; and 
 forming the dielectric layer over the second etch stop layer. 
 
     
     
       17. The method of  claim 16 , wherein
 forming a first trench in the dielectric layer comprises etching through the dielectric layer, the second etch stop layer and the first etch stop layer; and 
 forming the one or more second trenches in the dielectric layer comprises etching through the dielectric layer and stopping etching in the second etch stop layer. 
 
     
     
       18. The method of  claim 11 , wherein forming the first trench in the dielectric layer comprises a first etching step followed by a second etching step resulting in the first trench comprising a stair step profile. 
     
     
       19. The method of  claim 11 , wherein forming the first trench in the dielectric layer and forming the one or more second trenches in the dielectric layer comprises:
 a first etching step partially forming the first trench and forming the one or more second trenches; 
 filling the one or more second trenches with a photoresist layer; and 
 etching the partially formed first trench to complete the first trench. 
 
     
     
       20. The method of  claim 11 , further comprising:
 forming a passivation layer over the first blocking layer; and 
 forming a capacitor etch stop layer over the passivation layer.