Semiconductor devices with backside power rail and methods of fabrication thereof

Abstract

Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.

The invention claimed is: 
     
       1. A method for forming a semiconductor device, comprising:
 forming a semiconductor fin on a semiconductor substrate; 
 forming an isolation layer to cover a portion of the semiconductor fin; 
 forming a contact alignment feature in the portion of semiconductor fin covered by the isolation layer; 
 forming a first source/drain feature and a second source/drain feature over the semiconductor fin, wherein the first source/drain feature is aligned with the contact alignment feature; 
 after forming the first and second source/drain features, removing the portion of the semiconductor fin in the isolation layer; 
 forming a sacrificial liner to cover vertical sidewalls of the isolation layer and the contact alignment feature; and 
 performing an etch process to expose the second source/drain feature with the sacrificial liner covering the sidewalls of the isolation layer and the alignment feature. 
 
     
     
       2. The method of  claim 1 , wherein performing an etch process comprises recess etching the second source/drain feature. 
     
     
       3. The method of  claim 2 , further comprising:
 removing the sacrificial liner; and 
 forming a spacer liner over the second source/drain feature. 
 
     
     
       4. The method of  claim 3 , further comprising:
 removing the contact alignment feature to expose the first source/drain feature; and 
 forming a conductive feature over the first source/drain feature. 
 
     
     
       5. The method of  claim 3 , further comprising depositing a fill dielectric material over the spacer liner. 
     
     
       6. The method of  claim 2 , wherein the recess etching the second source/drain feature comprises recess etching the second source/drain feature to expose a portion of an inner spacer formed between the second source/drain feature and a gate structure. 
     
     
       7. The method of  claim 1 , where forming the semiconductor fin comprises:
 forming a semiconductor stack on a front side of the substrate, wherein the semiconductor stack comprises:
 two or more first semiconductor layers; and 
 two or more second semiconductor layers alternatively stacked with the first semiconductive layer; and 
 
 etching the semiconductor stack and a portion of the substrate to form the semiconductor fin. 
 
     
     
       8. The method of  claim 7 , further comprising: prior to removing a portion of semiconductor fin in contact with the isolation layer,
 removing the two or more first semiconductor layers disposed between the first and second source/drain features; 
 forming a gate dielectric layer on the two or more semiconductor layers disposed the first and second source/drain features; and 
 forming a gate electrode layer on the gate dielectric layer. 
 
     
     
       9. The method of  claim 8 , further comprising:
 forming a front contact feature in connection with the second source/drain feature. 
 
     
     
       10. The method of  claim 1 , wherein forming the sacrificial liner comprises:
 depositing a conformal layer over all exposed surfaces; and 
 anisotropically etching the conformal layer to expose horizontal surfaces. 
 
     
     
       11. The method of  claim 10 , wherein the sacrificial liner comprises a metal oxide. 
     
     
       12. A method, comprising:
 processing a front side of a substrate to form a structure comprising:
 a first source/drain feature; 
 a second source/drain feature; 
 a semiconductor channel between the first and second source drain features; 
 a gate dielectric layer on the semiconductor channel; and 
 an inner spacer formed between the gate dielectric layer and the second source/drain feature; 
 
 processing a back side of the substrate for form:
 a spacer liner in contact with the inner spacer, the gate dielectric layer, and a top surface of the second source/drain feature; and 
 a first conductive feature formed on a top surface of the first source/drain feature, wherein the top surface of the first source/drain feature is higher than the top surface of the second source/drain feature. 
 
 
     
     
       13. The method of  claim 12 , further comprising depositing a fill dielectric material formed over the spacer liner. 
     
     
       14. The method of  claim 12 , wherein the first source/drain feature contacts the first conductive feature along a first surface, the second source/drain feature contacts the spacer liner along a second surface, and the first surface and the second surface are at different levels. 
     
     
       15. The method of  claim 12 , further comprising:
 forming a first hybrid fin and a second hybrid fin parallel to the first hybrid fin, wherein the first source/drain feature, the second source/drain feature, and the semiconductor channel are disposed between the first and second hybrid fins, and the spacer liner is in contact with sidewalls of the first and second hybrid fins. 
 
     
     
       16. The method of  claim 12 , wherein processing the front side of the substrate further comprises forming a second conductive feature in contact with the second source/drain feature. 
     
     
       17. A method for forming a semiconductor device, comprising:
 forming a semiconductor fin on a semiconductor substrate; 
 forming an isolation layer to cover a portion of the semiconductor fin; 
 forming first and second dielectric fins in contact with the isolation layer; 
 forming first source/drain feature and second source/drain features between the first and second dielectric fins; and 
 forming a dielectric feature in contact with the second source/drain feature, wherein the dielectric feature includes a first portion formed in the isolation layer, and a second portion formed between the first and second dielectric fins, and the second portion is wider than the first portion; and 
 forming a first conductive feature in the isolation layer and extending between the first and second dielectric fins to contact the first source/drain feature. 
 
     
     
       18. The method of  claim 17 , wherein forming the dielectric feature comprising:
 depositing a spacer liner; and 
 depositing a fill dielectric material over the spacer liner, wherein the spacer liner contacts the sidewalls of the first and second dielectric fins. 
 
     
     
       19. The method of  claim 17 , further comprising:
 forming two or more semiconductor channels from a portion of the semiconductor fin, wherein the semiconductor channel is in contact with the first and second sourced/drain feature; and 
 forming a gate dielectric layer surrounding the two or more semiconductor channels, wherein the dielectric feature is in contact with the gate dielectric layer. 
 
     
     
       20. The method of  claim 19 , further comprising
 forming inner spacers between the two or more semiconductor channels, wherein the dielectric feature is in contact with one of the inner spacers.