Semiconductor device with cut metal gate and method of manufacture

Abstract

An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a first fin and a second fin protruding from a semiconductor substrate; 
 an isolation region over the semiconductor substrate between the first fin and the second fin; 
 a first metal gate stack over the first fin and the isolation region; 
 a second metal gate stack over the second fin, and the isolation region; and 
 a cut-metal gate plug between the first metal gate stack and the second metal gate stack, the cut-metal gate plug extending through the isolation region and into the semiconductor substrate, wherein a portion of the semiconductor substrate is in physical contact with a first sidewall of a first portion of the cut-metal gate plug and a second sidewall of a second portion of the cut-metal gate plug, and wherein the first portion of the cut-metal gate plug is separated from the second portion of the cut-metal gate plug by the portion of the semiconductor substrate. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first metal gate stack is a gate electrode of an n-type device, and wherein the second metal gate stack is a gate electrode of a p-type device. 
     
     
       3. The semiconductor device of  claim 1 , wherein the cut-metal gate plug comprises silicon nitride or silicon carbon nitride. 
     
     
       4. The semiconductor device of  claim 1 , wherein the cut-metal gate plug extends into the semiconductor substrate from a bottom surface of the isolation region by a distance equal to or less than 40 nm. 
     
     
       5. The semiconductor device of  claim 1 , wherein a top portion of the cut-metal gate plug is wider than a bottom portion of the cut-metal gate plug. 
     
     
       6. The semiconductor device of  claim 1 , further comprising an isolation layer over the first metal gate stack and the second metal gate stack, wherein the isolation layer is in physical contact with the cut-metal gate plug. 
     
     
       7. The semiconductor device of  claim 6 , wherein the isolation layer has a same composition as the cut-metal gate plug. 
     
     
       8. A semiconductor device comprising:
 a semiconductor substrate and a first dielectric layer over the semiconductor substrate; 
 a first fin and a second fin protruding from the semiconductor substrate; 
 a first source/drain region over the first fin and a second source/drain region over the second fin; 
 a second dielectric layer over the first fin, the first source/drain region, the second fin, the second source/drain region, and the first dielectric layer; and 
 an isolation feature between the first source/drain region and the second source/drain region, the isolation feature extending through the second dielectric layer, through the first dielectric layer, and into the semiconductor substrate, wherein a first portion of the isolation feature in the semiconductor substrate has a first width, wherein a second portion of the isolation feature in the second dielectric layer has a second width, and wherein the first width is smaller than the second width. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein the first source/drain region is a source/drain region of an n-type device, and wherein the second source/drain region is a source/drain region of a p-type device. 
     
     
       10. The semiconductor device of  claim 8 , wherein the isolation feature comprises a silicon-containing dielectric material. 
     
     
       11. The semiconductor device of  claim 8 , wherein the isolation feature extends into the semiconductor substrate by no more than 40 nm. 
     
     
       12. The semiconductor device of  claim 8 , wherein the semiconductor substrate comprises a first doped region containing a first dopant of a first conductivity type and a second doped region containing a second dopant of a second conductivity type, wherein the first conductivity type is different from the second conductivity type, and wherein the isolation feature overlies an interface between the first doped region and the second doped region. 
     
     
       13. The semiconductor device of  claim 8 , wherein the isolation feature comprises a third portion, wherein the first portion of the isolation feature is disposed in a first recess of the semiconductor substrate and the third portion of the isolation feature is disposed in a second recess of the semiconductor substrate, and wherein the first recess is separate from the second recess. 
     
     
       14. A semiconductor device comprising:
 a semiconductor substrate, wherein the semiconductor substrate comprises a first doped region containing a p-type dopant and a second doped region containing an n-type dopant; 
 a first fin over the first doped region and a second fin over the second doped region; 
 an isolation region over the semiconductor substrate between the first fin and the second fin; 
 a first source/drain region over the first fin and a second source/drain region over the second fin; 
 a dielectric layer over the first fin, the first source/drain region, the second fin, the second source/drain region, and the isolation region; and 
 an dielectric plug between the first fin and the second fin, the dielectric plug extending through the dielectric layer, through the isolation region, and into the semiconductor substrate, wherein a first portion of the dielectric plug is disposed in a first recess of the semiconductor substrate and a second portion of the dielectric plug is disposed in a second recess of the semiconductor substrate, and wherein the first recess is spaced apart from the second recess. 
 
     
     
       15. The semiconductor device of  claim 14 , wherein the first portion of the dielectric plug has a first width and a third portion of the dielectric plug disposed in the dielectric layer and over the first portion has a second width, and wherein the first width is smaller than the second width. 
     
     
       16. The semiconductor device of  claim 14 , wherein the dielectric plug extends to an interface between the first doped region and the second doped region. 
     
     
       17. The semiconductor device of  claim 14 , further comprising an isolation layer over the dielectric layer and the dielectric plug, wherein the isolation layer has a same composition as the dielectric plug. 
     
     
       18. The semiconductor device of  claim 17 , further comprising a source/drain contact structure, wherein the source/drain contact structure extends through the isolation layer and into the dielectric layer. 
     
     
       19. The semiconductor device of  claim 18 , wherein the source/drain contact structure contacts the dielectric plug. 
     
     
       20. The semiconductor device of  claim 19 , wherein the source/drain contact structure contacts the first source/drain region and the second source/drain region.