Through-substrate-via with reentrant profile

Abstract

The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance.

What is claimed is: 
     
       1. An integrated chip, comprising:
 a semiconductor device arranged along a first side of a semiconductor substrate, wherein the semiconductor substrate comprises one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate; 
 a dielectric liner lining the one or more sidewalls of the semiconductor substrate; 
 a through-substrate-via (TSV) arranged between the one or more sidewalls and separated from the semiconductor substrate by the dielectric liner; and 
 wherein the dielectric liner has sidewalls that slope inward towards one another from an upper surface of the dielectric liner arranged directly below the TSV to a topmost surface of the dielectric liner over the one or more sidewalls of the semiconductor substrate, so that the dielectric liner overhangs the TSV in a cross-sectional view. 
 
     
     
       2. The integrated chip of  claim 1 , wherein the TSV continuously contacts the sidewalls of the dielectric liner between the first side and the second side of the semiconductor substrate. 
     
     
       3. The integrated chip of  claim 1 , wherein the dielectric liner comprises a first sidewall and a second sidewall facing opposing sides of the TSV and a horizontally extending ledge protruding outward from the first sidewall and towards the second sidewall. 
     
     
       4. The integrated chip of  claim 3 , further comprising:
 an etch blocking layer arranged between the dielectric liner and sidewalls of the TSV, wherein the etch blocking layer has a bottom that is separated from the horizontally extending ledge of the dielectric liner. 
 
     
     
       5. The integrated chip of  claim 4 , further comprising:
 an etch blocking layer remnant disposed along the upper surface and one of the sidewalls of the dielectric liner, the etch blocking layer being separated from the etch blocking layer remnant by the TSV. 
 
     
     
       6. The integrated chip of  claim 4 , further comprising:
 a dielectric layer disposed between the second side of the semiconductor substrate and a lower surface of the dielectric liner facing the second side of the semiconductor substrate, wherein the TSV has a minimum width over a top of the dielectric layer facing away from the semiconductor substrate. 
 
     
     
       7. The integrated chip of  claim 1 , wherein the upper surface of the dielectric liner is parallel to the first side of the semiconductor substrate. 
     
     
       8. The integrated chip of  claim 7 , further comprising:
 a plurality of interconnects disposed within an inter-level dielectric (ILD) structure arranged along the first side of the semiconductor substrate, 
 wherein the TSV comprises a horizontally extending surface facing away from the semiconductor substrate and a protrusion extending outward from the horizontally extending surface, the protrusion extending through the ILD structure to contact one of the plurality of interconnects. 
 
     
     
       9. The integrated chip of  claim 1 , wherein the one or more sidewalls of the semiconductor substrate are respectively defined by a plurality of curved depressions. 
     
     
       10. An integrated chip, comprising:
 a plurality of interconnects disposed within an inter-level dielectric (ILD) structure arranged along a first side of a substrate; 
 an etch stop layer arranged along the first side of the substrate; 
 a through-substrate-via (TSV) extending through the substrate and the etch stop layer; 
 a dielectric liner separating the TSV from the substrate, wherein the dielectric liner is along sidewalls of the substrate and the etch stop layer and wherein the dielectric liner comprises a first sidewall and a second sidewall facing opposing sides of the TSV and a horizontally extending ledge protruding outward from the first sidewall and towards the second sidewall; and 
 wherein the TSV comprises a horizontally extending surface disposed on the horizontally extending ledge of the dielectric liner and a protrusion extending outward from the horizontally extending surface to one of the plurality of interconnects. 
 
     
     
       11. The integrated chip of  claim 10 , wherein the dielectric liner continuously extends from along the sidewalls of the substrate to along a second side of the substrate opposing the first side of the substrate. 
     
     
       12. The integrated chip of  claim 10 , further comprising:
 an etch blocking layer arranged between the dielectric liner and sidewalls of the TSV, wherein the etch blocking layer is vertically separated from the horizontally extending ledge of the dielectric liner by a non-zero distance. 
 
     
     
       13. The integrated chip of  claim 12 , wherein the protrusion of the TSV has a width that is larger than a minimum distance between interior sidewalls of the etch blocking layer that face one another. 
     
     
       14. The integrated chip of  claim 12 ,
 wherein the etch blocking layer has sidewalls facing the TSV; and 
 wherein the sidewalls of the etch blocking layer are separated by a first distance and the protrusion has a width that is greater than or equal to the first distance. 
 
     
     
       15. The integrated chip of  claim 10 , wherein the dielectric liner extends from along the sidewalls of the substrate to a top of the TSV. 
     
     
       16. The integrated chip of  claim 10 , wherein the first sidewall of the dielectric liner is separated from the horizontally extending ledge of the dielectric liner by an angle of between approximately 80° and approximately 90°. 
     
     
       17. The integrated chip of  claim 10 ,
 wherein the TSV has a first sidewall that is directly between the sidewalls of the substrate and that has a first slope; and 
 wherein the TSV has a second sidewall that is directly between sidewalls of the ILD structure and that has a second slope that is larger than the first slope. 
 
     
     
       18. A method of forming an integrated chip, comprising:
 forming a plurality of interconnects within an inter-level dielectric (ILD) structure along a first side of a substrate; 
 forming a masking layer on a second side of the substrate opposing the first side; 
 performing a first etching process to etch the substrate according to the masking layer and to form sidewalls of the substrate that define a first through-substrate-via (TSV) opening extending through the substrate, wherein the first TSV opening has a width that increases as a distance from the masking layer increases; 
 forming a dielectric liner along the sidewalls of the substrate and on the ILD structure; 
 performing a second etching process on the dielectric liner and the ILD structure to form a second TSV opening exposing one of the plurality of interconnects, wherein the second TSV opening is separated from a sidewall of the dielectric liner by a non-zero distance; and 
 forming a through-substrate-via (TSV) within the first TSV opening and the second TSV opening, wherein the dielectric liner has sidewalls that slope inward towards one another from an upper surface of the dielectric liner arranged directly below the TSV to a topmost surface of the dielectric liner over the sidewalls of the substrate, as viewed in a cross-sectional view. 
 
     
     
       19. The method of  claim 18 , further comprising:
 forming an etch blocking layer on the sidewalls of the dielectric liner, wherein the second etching process etches the dielectric liner and the ILD structure according to the etch blocking layer; and 
 wherein an etch blocking layer remnant is disposed along the upper surface and one of the sidewalls of the dielectric liner after forming the etch blocking layer, the etch blocking layer being separated from the etch blocking layer remnant by the TSV. 
 
     
     
       20. The method of  claim 18 , further comprising:
 forming an etch stop layer along the first side of the substrate, wherein the first etching process etches through the etch stop layer so that the first TSV opening is formed by the sidewalls of the substrate and the etch stop layer.