Semiconductor device including epitaxial region

Abstract

A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a substrate; 
 an isolation layer on the substrate; 
 an active region penetrating through the isolation layer and extending in a first direction; 
 a source/drain on a first portion of the active region; 
 an interlayer insulating layer on the isolation layer and the source/drain; 
 a contact structure penetrating through the interlayer insulating layer and contacting the source/drain; and 
 an insulating spacer between the interlayer insulating layer and the contact structure, 
 wherein the source/drain includes:
 a base epitaxial region on the first portion of the active region; 
 a first epitaxial region on the base epitaxial region and having a recessed surface; and 
 a second epitaxial region on the recessed surface of the first epitaxial region, 
 
 wherein the second epitaxial region vertically overlaps the insulating spacer and the contact structure, 
 wherein an upper end of the first epitaxial region is at a higher level than an upper end of the second epitaxial region, 
 wherein the insulating spacer contacts the first epitaxial region and the second epitaxial region, and 
 wherein the first direction is parallel to an upper surface of the substrate. 
 
     
     
       2. The semiconductor device of  claim 1 ,
 wherein the contact structure includes a metal-semiconductor compound layer and a contact plug on the metal-semiconductor compound layer, and 
 wherein the metal-semiconductor compound layer contacts the second epitaxial region. 
 
     
     
       3. The semiconductor device of  claim 2 , wherein the metal-semiconductor compound layer is spaced apart from the first epitaxial region. 
     
     
       4. The semiconductor device of  claim 2 , wherein a lower surface of the metal-semiconductor compound layer is at a lower level than an upper end of the first epitaxial region. 
     
     
       5. The semiconductor device of  claim 2 , wherein an upper surface of the metal-semiconductor compound layer is at a higher level than a lower end of the insulating spacer. 
     
     
       6. The semiconductor device of  claim 1 ,
 wherein the second epitaxial region includes a lower portion and an upper portion on the lower portion, 
 wherein the lower portion of the second epitaxial region is at a lower level than a lower end of the insulating spacer, and 
 wherein the upper portion of the second epitaxial region is at a higher level than the lower end of the insulating spacer. 
 
     
     
       7. The semiconductor device of  claim 6 , wherein at least a portion of an upper surface of the upper portion of the second epitaxial region has an upwardly convex shape. 
     
     
       8. The semiconductor device of  claim 6 , wherein at least a portion of an upper surface of the upper portion of the second epitaxial region has a downwardly concave shape. 
     
     
       9. The semiconductor device of  claim 6 , wherein the upper portion of the second epitaxial region includes a first inclined surface and a second inclined surface different from the first inclined surface. 
     
     
       10. The semiconductor device of  claim 6 ,
 wherein a maximum width of the lower portion is greater than a maximum width of the upper portion in a second direction, and 
 wherein the second direction is parallel to the upper surface of the substrate and is perpendicular to the first direction. 
 
     
     
       11. The semiconductor device of  claim 1 , further comprising:
 a gate structure on a second portion of the active region and extending in a second direction; and 
 a plurality of active layers spaced apart from each other in a vertical direction and on a second portion of the active region, 
 wherein the second direction is parallel to the upper surface of the substrate and is perpendicular to the first direction, 
 wherein the vertical direction is perpendicular to the upper surface of the substrate, 
 wherein the gate structure covers an upper surface, a side surface, and a lower surface of each of the plurality of active layers, and 
 wherein the gate structure includes a gate electrode and a gate dielectric layer between the gate electrode and the plurality of active layers. 
 
     
     
       12. A semiconductor device, comprising:
 a substrate; 
 an isolation layer on the substrate; 
 an active region penetrating through the isolation layer and extending in a first direction; 
 a source/drain on a first portion of the active region; 
 an interlayer insulating layer on the isolation layer and the source/drain; 
 a contact hole penetrating through the interlayer insulating layer and exposing the source/drain; and 
 a contact structure in the contact hole and contacts the source/drain, 
 wherein the first direction is parallel to an upper surface of the substrate, 
 wherein the source/drain includes:
 a base epitaxial region on the first portion of the active region; 
 a first epitaxial region on the base epitaxial region and having a recessed surface; and 
 a second epitaxial region on the recessed surface of the first epitaxial region, 
 
 wherein the second epitaxial region includes a lower portion and an upper portion on the lower portion, 
 wherein the lower portion of the second epitaxial region is at a lower level than the contact hole, 
 wherein the upper portion of the second epitaxial region extends in a lower region of the contact hole from the lower portion of the second epitaxial region, and contacts the contact structure, 
 wherein a maximum width in a second direction of the lower portion is greater than a maximum width in the second direction of the upper portion, 
 wherein the second direction is perpendicular to the first direction and is parallel to the upper surface of the substrate, and 
 wherein an upper end of the first epitaxial region is at a higher level than a lower end of the second epitaxial region. 
 
     
     
       13. The semiconductor device of  claim 12 ,
 wherein the contact structure includes a metal-semiconductor compound layer and a contact plug on the metal-semiconductor compound layer, and 
 wherein the metal-semiconductor compound layer contacts the upper portion of the second epitaxial region and is spaced apart from the first epitaxial region. 
 
     
     
       14. The semiconductor device of  claim 12 , wherein an upper end of the first epitaxial region is at a lower level than an upper end of the second epitaxial region. 
     
     
       15. The semiconductor device of  claim 12 , further comprising:
 an insulating spacer, 
 wherein the insulating spacer includes: 
 a first spacer portion contacting the contact structure and between the contact structure and a sidewall of an upper region of the contact hole, and 
 a second spacer portion contacting the second epitaxial region and between the upper portion of the second epitaxial region and a sidewall of the lower region of the contact hole. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein the insulating spacer further includes a third spacer portion extending downward from the second spacer portion and contacting the first epitaxial region. 
     
     
       17. The semiconductor device of  claim 12 , further comprising:
 a gate structure on a second portion of the active region and extending in the second direction; and 
 a plurality of active layers spaced apart from each other in a vertical direction and on a second portion of the active region, 
 wherein the vertical direction is perpendicular to the upper surface of the substrate, 
 wherein the gate structure covers an upper surface, a side surface, and a lower surface of each of the plurality of active layers, and 
 wherein the gate structure includes a gate electrode and a gate dielectric layer between the gate electrode and the plurality of active layers. 
 
     
     
       18. A semiconductor device, comprising:
 a substrate; 
 an isolation layer on the substrate; 
 an active region penetrating through the isolation layer and extending in a first direction; 
 a source/drain on a first portion of the active region; 
 a plurality of active layers on a second portion of the active region and spaced apart from each other in a vertical direction; 
 a gate structure on the second portion of the active region, and covering an upper surface, a side surface, and a lower surface of each of the plurality of active layers; 
 an interlayer insulating layer on the isolation layer and the source/drain; 
 a contact structure penetrating through the interlayer insulating layer and contacting the source/drain; and 
 an insulating spacer between the interlayer insulating layer and the contact structure, 
 wherein the source/drain includes:
 a base epitaxial region on the first portion of the active region; 
 a first epitaxial region on the base epitaxial region and having a recessed surface; and 
 a second epitaxial region on the recessed surface of the first epitaxial region, 
 
 wherein the second epitaxial region vertically overlaps the insulating spacer and the contact structure, 
 wherein the plurality of active layers include a lower active layer, an intermediate active layer on the lower active layer, and an upper active layer on the intermediate active layer, 
 wherein the contact structure includes a metal-semiconductor compound layer and a contact plug on the metal-semiconductor compound layer, 
 wherein the metal-semiconductor compound layer contacts the second epitaxial region and is spaced apart from the first epitaxial region, 
 wherein a lower end of the second epitaxial region is at a lower level than a lower surface of the upper active layer, 
 wherein an upper end of the first epitaxial region is at a higher level than the lower surface of the upper active layer, and 
 wherein the first direction is parallel to an upper surface of the substrate. 
 
     
     
       19. The semiconductor device of  claim 18 , wherein an upper surface of the second epitaxial region is at a lower level than an upper surface of the upper active layer. 
     
     
       20. The semiconductor device of  claim 18 ,
 wherein a lower end of the first epitaxial region is at a lower level than a lower surface of the intermediate active layer, and 
 wherein a lower end of the second epitaxial region is at a higher level than the lower surface of the intermediate active layer.