Fin field-effect transistor and method of forming the same

Abstract

A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.

What is claimed is: 
     
       1. A method, comprising:
 forming a gate trench over a semiconductor fin, the gate trench including a top portion over a bottom portion that is narrower than the top portion; 
 depositing a glue layer in the gate trench, the glue layer including a second sub-layer over a first sub-layer, wherein the first and the second sub-layers differ in composition, and wherein a portion of the first sub-layer completely fills the bottom portion of the gate trench; and 
 removing a portion of the glue layer from the top portion of the gate trench to expose the portion of the first sub-layer in the bottom portion of the gate trench. 
 
     
     
       2. The method of  claim 1 , further comprising, before depositing the glue layer:
 depositing at least one work function layer in the gate trench; and 
 depositing a capping layer over the at least one work function layer, wherein the step of removing the portion of the glue layer exposes a portion of the capping layer in the top portion of the gate trench. 
 
     
     
       3. The method of  claim 2 , further comprising:
 removing the portion of the capping layer from the top portion of the gate trench, resulting in a recess that extends into the bottom portion of the gate trench; and 
 removing a portion of the at least one work function layer from the top portion of the gate trench to form a metal gate in the bottom portion of the gate trench. 
 
     
     
       4. The method of  claim 3 , further comprising depositing a metal material in the recess to form a gate electrode overlaying the metal gate. 
     
     
       5. The method of  claim 1 , wherein:
 the step of depositing the glue layer results in an entirety of the second sub-layer to be deposited in the top portion of the gate trench; and 
 the step of removing the portion of the glue layer removes the entirety of the second sub-layer from the top portion of the gate trench. 
 
     
     
       6. The method of  claim 1 , wherein the step of removing the portion of the glue layer is implemented by a wet etching process that utilizes a mixture of ammonium hydroxide (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) as an etching solution. 
     
     
       7. The method of  claim 6 , wherein an etching rate of the second sub-layer is greater than an etching rate of the first sub-layer. 
     
     
       8. The method of  claim 1 , further comprising, before forming the gate trench:
 forming a dummy gate structure over the semiconductor fin; 
 forming first gate spacers on sidewalls of the dummy gate structure; and 
 forming second gate spacers over the first gate spacers, wherein the step of forming the gate trench includes removing the dummy gate structure between the second gate spacers such that the top portion of the gate trench is surrounded by only the second gate spacers and the bottom portion of the gate trench is surrounded by both the first and the second gate spacers. 
 
     
     
       9. The method of  claim 1 , wherein the first sub-layer includes tantalum nitride and the second sub-layer includes titanium nitride. 
     
     
       10. A method, comprising:
 forming a trench over a channel region of a semiconductor layer, the trench having an upper portion over a lower portion; 
 forming a first glue layer in the trench, the first glue layer having a first portion formed in the upper portion of the trench and a second portion formed in the lower portion of the trench; 
 forming a second glue layer over the first glue layer, an entirety of the second glue layer being formed in the upper portion of the trench; and 
 performing an etching process to remove the second glue layer and the first portion of the first glue layer, thereby exposing the second portion of the first glue layer. 
 
     
     
       11. The method of  claim 10 , further comprising, before depositing the first glue layer:
 forming a work function layer in the gate trench; and 
 forming a capping layer over the work function layer, wherein the step of removing the second glue layer and the first portion of the first glue layer exposes a portion of the capping layer in the upper portion of the gate trench. 
 
     
     
       12. The method of  claim 11 , further comprising:
 removing the portion of the capping layer and a portion of the work function layer from the top portion of the gate trench, resulting in a recess that extends into the lower portion of the gate trench; and 
 depositing a metal material in the recess to form a gate electrode overlaying remaining portions of the capping layer and the work function layer in the lower portion of the gate trench. 
 
     
     
       13. The method of  claim 10 , wherein the step of removing the second glue layer and the first portion of the first glue layer includes performing a wet etching process that utilizes a mixture of ammonium hydroxide (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) as an etchant. 
     
     
       14. The method of  claim 13 , wherein the first glue layer has a first etching rate with respect to the etchant and the second glue layer has a second etching rate with respect to the etchant, and wherein the first etching rate is less than the second etching rate. 
     
     
       15. The method of  claim 13 , wherein a ratio of a volume of NH 4 OH to a volume of H 2 O 2  is between about 1:1 and about 1:10. 
     
     
       16. The method of  claim 10 , wherein the first glue layer includes tantalum nitride and the second glue layer includes titanium nitride. 
     
     
       17. A method, comprising:
 forming a trench over a channel region of a semiconductor layer, the trench having an upper portion over a lower portion; 
 forming a work function layer in the trench; 
 forming a capping layer over the work function layer; 
 forming a first glue layer over the capping layer, the first glue layer having a first portion formed in the upper portion of the trench and a second portion completely filling the lower portion of the trench; 
 forming a second glue layer over the first portion of the first glue layer; and 
 performing an etching process to remove the second glue layer and the first portion of the first glue layer, thereby exposing the capping layer and the second portion of the first glue layer. 
 
     
     
       18. The method of  claim 17 , wherein the etching process is a first etching process, further comprising:
 performing a second etching process to remove the capping layer from the upper portion of the trench, resulting in a recess that extends into the lower portion of the gate trench; 
 performing a third etching process to remove the work function layer from the upper portion of the trench to form a metal gate in the lower portion of the gate trench; and 
 depositing a conductive layer in the recess to form a gate electrode overlaying the metal gate. 
 
     
     
       19. The method of  claim 18 , wherein the first, the second, and the third etching processes are each a wet etching process, and wherein the second etching process results in the work function layer, the capping layer, and the second portion of the first glue layer to collectively have a curved upper surface. 
     
     
       20. The method of  claim 17 , wherein the first glue layer includes tantalum nitride and the second glue layer includes titanium nitride.