Composite interconnect formation using graphene

Abstract

A semiconductor fabrication method that uses a graphene etch stop is disclosed. The method comprises forming a first set of trenches and a second set of trenches in a substrate. The first set of trenches are narrower than the second set of trenches. The method further comprises forming a graphene layer in the first and second sets of trenches. The method further comprises depositing a first conductor in the first and second sets of trenches. The method further comprises removing the first conductor from the second set of trenches using an etching process. The graphene layer acts as an etch stop for the etching process. The method further comprises depositing a second conductor in the second set of trenches. The second conductor is different than the first conductor.

What is claimed is: 
     
       1. A semiconductor structure comprising:
 a substrate; 
 a first set of lines formed in the substrate, wherein the first set of lines includes a first conductor material; 
 a second set of lines formed in the substrate, the second set of lines having a width that is larger than the first set of lines, wherein the second set of lines includes a second conductor material, 
 wherein the second set of lines are separated from the substrate by a graphene liner material, and 
 wherein the first and second sets of lines are interconnects. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein the first set of lines are separated from the substrate by the graphene liner material. 
     
     
       3. The semiconductor structure of  claim 1 , further comprising:
 an adhesion layer in direct contact with the substrate; and 
 a catalytic layer in direct contact with the adhesion layer opposite the substrate, 
 wherein the adhesion layer is disposed between the substrate and the catalytic layer, and the catalytic layer is disposed between the adhesion layer and the graphene liner material. 
 
     
     
       4. The semiconductor structure of  claim 3 , wherein the adhesion layer has a thickness of between approximately 5 A and approximately 400 A. 
     
     
       5. The semiconductor structure of  claim 3 , wherein the catalytic layer is selected from the group consisting of Co, Ru, Ni, Pt, and Ir. 
     
     
       6. The semiconductor structure of  claim 1 , wherein the first conductor material is selected from the group consisting of Ru and Co, and wherein the second conductor material is selected from the group consisting of W, Cu, Al, Ta, and Rh. 
     
     
       7. The semiconductor structure of  claim 1 , wherein each line of the first and second sets of lines is electrically isolated from all other lines.