Gate-all-around structure with self substrate isolation and methods of forming the same

Abstract

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.

What is claimed is: 
     
       1. A method comprising:
 forming a fin structure over a substrate, wherein the fin structure includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer, wherein a doping concentration of the second semiconductor layer is greater than a doping concentration of the substrate; 
 removing a first portion of the third semiconductor layer and a first portion of the fourth semiconductor layer to form a first recess in the fin structure; 
 forming a source/drain feature in the first recess; 
 removing a first portion of the first semiconductor layer and a second portion of the third semiconductor layer to form a first gap between the substrate and the second semiconductor layer and a second gap between the second semiconductor layer and a second portion of the fourth semiconductor layer, wherein the first gap extends under the source/drain feature after the removing of the first portion of the first semiconductor layer and the second portion of the third semiconductor layer to form the first gap; 
 forming a first gate dielectric in the first gap and the second gap, wherein the first gate dielectric fills the first gap and wherein the first gate dielectric wraps around the second portion of the fourth semiconductor layer and partially fills the second gap; and 
 forming a gate electrode on the first gate dielectric in the second gap. 
 
     
     
       2. The method of  claim 1 , wherein a thickness of the first semiconductor layer is different than a thickness of the third semiconductor layer. 
     
     
       3. The method of  claim 1 , further comprising forming a second gate dielectric layer on the fin structure prior to the removing of the third semiconductor layer and the fourth semiconductor to form a first recess in the fin structure. 
     
     
       4. The method of  claim 1 , wherein the removing of the first semiconductor layer and the third semiconductor layer to form the first gap between the substrate and the second semiconductor layer and the second gap between the second semiconductor layer and the fourth semiconductor layer includes performing an oxidation process. 
     
     
       5. The method of  claim 1 , further comprising forming an inner spacer layer on the second portion of the third semiconductor layer. 
     
     
       6. The method of  claim 1 , wherein the second semiconductor layer is exposed within the first recess after the removing of the first portion of the third semiconductor layer and the first portion of the fourth semiconductor layer to form the first recess in the fin structure. 
     
     
       7. The method of  claim 1 , wherein the second semiconductor layer interfaces with the first semiconductor layer, the third semiconductor layer interfaces with the second semiconductor layer and the fourth semiconductor layer interfaces with the third semiconductor layer after the forming of the fin structure over the substrate. 
     
     
       8. The method of  claim 1 , wherein the forming of the source/drain feature in the first recess includes forming the source/drain feature over a portion of the second semiconductor layer that is disposed under the source/drain feature, and
 wherein the portion of the second semiconductor layer disposed under the source/drain feature is exposed to the first gap. 
 
     
     
       9. A method comprising:
 forming a first material layer over a substrate; 
 forming a second material layer over the first material layer, the second material layer being formed of a different material than the first material layer; 
 forming a third material layer over the second material layer; 
 forming a fourth material layer over the third material layer, the third material layer being formed of a different material than the fourth material layer; 
 forming a recess in the fourth material layer and the third material layer, the third material layer being exposed in the recess; 
 removing a first portion of the third material layer exposed in the recess such that a second portion of the third material layer remains after the removing of the first portion of the third material layer; 
 forming an sidewall spacer on the second portion of the third material layer; 
 forming a source/drain feature in the recess; 
 removing the first material layer to form a first gap between the substrate and the second material layer, the first gap extending under the source/drain feature; and 
 forming a first dielectric material in the first gap such that the first dielectric material fills the first gap. 
 
     
     
       10. The method of  claim 9 , wherein the forming of the sidewall spacer on the second portion of the third material layer includes forming the sidewall spacer directly on the second material layer, the second portion of the third material layer and the fourth material layer. 
     
     
       11. The method of  claim 9 , wherein the second material layer is an anti-punch through layer having a first dopant concentration, and
 wherein the substrate has a second dopant concentration that is less than the first dopant concentration. 
 
     
     
       12. The method of  claim 9 , wherein the first dielectric material includes an interfacial layer and a gate dielectric layer. 
     
     
       13. The method of  claim 9 , wherein the removing of the first material layer to form the first gap between the substrate and the second material layer further includes removing the second portion of the third material layer to form a second gap between the second semiconductor layer and the fourth semiconductor layer. 
     
     
       14. The method of  claim 13 , wherein the forming of the first dielectric material in the first gap includes forming the first dielectric material in the second gap, the method further comprising;
 forming a gate electrode on the first dielectric material in the second gap. 
 
     
     
       15. The method of  claim 9 , wherein the forming of the source/drain feature in the recess includes forming the source/drain feature directly on the second material layer. 
     
     
       16. The method of  claim 15 , wherein a portion of the second material layer disposed under the source/drain feature is exposed to the first gap after the removing of the first material layer to form the first gap between the substrate and the second material layer. 
     
     
       17. A method of forming a semiconductor device, comprising:
 forming a fin structure over a substrate, wherein the fin structure includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, a third semiconductor layer over the second semiconductor layer, and a fourth semiconductor layer over the third semiconductor layer, wherein a thickness of the first semiconductor layer is less than a thickness of the third semiconductor layer and a doping concentration of the second semiconductor layer is greater than a doping concentration of the substrate; 
 forming a dummy gate structure over a first region of the fin structure; 
 removing the third semiconductor layer and the fourth semiconductor layer from a second region and a third region of the fin structure, wherein the first region is disposed between the second region and the third region; 
 forming a first source/drain (S/D) feature and a second S/D feature over the second semiconductor layer respectively in the second region and the third region; 
 removing the dummy gate structure to expose the first region of the fin structure; 
 selectively removing the first semiconductor layer and the third semiconductor layer to form a first gap between the substrate and the second semiconductor layer and a second gap between the second semiconductor layer and the fourth semiconductor layer; 
 forming a gate dielectric in the first gap and the second gap, wherein the gate dielectric fills the first gap, and further wherein the gate dielectric wraps the fourth semiconductor layer and partially fills the second gap; and 
 forming a gate electrode over the gate dielectric in the second gap. 
 
     
     
       18. The method of  claim 17 , wherein the forming the fin structure includes:
 depositing the first semiconductor layer including a first material over the substrate; 
 depositing the second semiconductor layer including a second material over the substrate; 
 performing an implantation process on the second semiconductor layer; 
 after the implantation process, depositing a third semiconductor layer including the first material over the second semiconductor layer; 
 depositing a fourth semiconductor layer including the second material over the third semiconductor layer; and 
 patterning the first, second, third, and fourth semiconductor layers to form the fin structure. 
 
     
     
       19. The method of  claim 17 , wherein the forming the gate dielectric in the first gap and the second gap includes:
 depositing a first dielectric material in the first and second gaps, wherein the first dielectric material wraps the second and fourth semiconductor layers in the first region; and 
 depositing a second dielectric material over the first dielectric material in the first and second gaps, wherein the first and second dielectric materials fill the second gap. 
 
     
     
       20. The method of  claim 17 , further comprising doping the fourth semiconductor layer with a doping concentration less than the doping concentration of the second semiconductor layer.