Long channel and short channel vertical FET co-integration for vertical FET VTFET

Abstract

A semiconductor including a short channel device including a vertical FET (Field-Effect Transistor), and a long channel device comprising a second vertical FET integrated with the short channel device. The long channel device including a plurality of short channel devices.

What is claimed is: 
     
       1. A semiconductor chip, comprising:
 a short channel device, wherein the short channel device is a vertical FET (Field-Effect Transistor) comprising:
 a bottom source-drain region; 
 a single fin; 
 a gate formed between a bottom spacer and a top spacer; 
 a top source-drain region formed on the top spacer; and 
 a metal contact formed on the top source-drain region; and 
 
 a long channel device, wherein the long channel device is a second vertical FET comprising:
 a plurality of fins, wherein sets of adjacent fins from the plurality of fins have connected bottom source-drain regions; 
 a plurality of gates formed between a second top spacer and a second bottom spacer, wherein the plurality of gates are physically separated from one another; 
 top source-drain regions formed on the second top spacer for each fin of the plurality of fins; and 
 a plurality of metal contacts connecting, for each of the sets, the top source-drain regions of the adjacent fins. 
 
 
     
     
       2. The semiconductor chip according to  claim 1 , further comprising:
 a single silicon substrate for both the long channel device and the short channel device, wherein the plurality of gates formed for the long channel device and the gate formed for the short channel device are formed on the substrate, each of the gates being physically separated by a dielectric material. 
 
     
     
       3. The semiconductor chip according to  claim 1 , further comprising wells formed and defining the bottom source region of the short channel device and the connected bottom source-drain regions of the long channel device. 
     
     
       4. The semiconductor chip of  claim 1 , wherein the gate of the short channel device and the plurality of gates of the long channel device have a same gate length. 
     
     
       5. The semiconductor chip of  claim 1 , further comprising a shallow trench isolation (STI) region. 
     
     
       6. The semiconductor chip of  claim 1 , wherein the long channel device is an input/output (I/O) device. 
     
     
       7. The semiconductor chip of  claim 1 , wherein the top source-drain regions of the adjacent fins are connected by a local interconnect. 
     
     
       8. The semiconductor chip of  claim 1 , wherein the plurality of fins comprises at least three sets of the adjacent fins. 
     
     
       9. The semiconductor chip of  claim 1 , further comprising a high K dielectric region around the plurality of gates. 
     
     
       10. A semiconductor device, comprising:
 a short channel device being vertically formed, the short channel device comprising:
 a bottom source-drain region; 
 a single fin; 
 a gate formed between a bottom spacer and a top spacer; 
 a top source-drain region formed on the top spacer; and 
 a metal contact formed on the top source-drain region; and 
 
 a long channel device being vertically formed on a same substrate as the short channel device, wherein the long channel device comprises:
 a plurality of fins, wherein sets of adjacent fins from the plurality of fins have connected bottom source-drain regions; 
 a plurality of gates formed between a second top spacer and a second bottom spacer, wherein the plurality of gates are physically separated from one another; 
 top source-drain regions formed on the second top spacer for each fin of the plurality of fins; and 
 a plurality of metal contacts connecting, for each of the sets, the top source-drain regions of the adjacent fins. 
 
 
     
     
       11. The semiconductor device according to  claim 10 , wherein
 the plurality of gates are physically separated by a dielectric material, and 
 wherein the short channel and the long channel devices have a same gate length. 
 
     
     
       12. The semiconductor device of  claim 10 , wherein the long channel device is an input/output (I/O) device. 
     
     
       13. The semiconductor device of  claim 10 , further comprising wells formed and defining the bottom source region of the short channel device and the connected bottom source-drain regions of the long channel device. 
     
     
       14. The semiconductor device of  claim 10 , further comprising a shallow trench isolation (STI) region. 
     
     
       15. The semiconductor device of  claim 10 , further comprising a high K dielectric region around the plurality of gates. 
     
     
       16. The semiconductor device of  claim 10 , wherein the plurality of fins comprises at least three sets of the adjacent fins. 
     
     
       17. A semiconductor device comprising:
 a shallow trench isolation (STI) region and a bottom source-drain region formed for a short channel device in a substrate, wherein the short channel device is a vertical field-effect transistor (FET) comprising:
 a single fin; 
 a gate formed between a bottom spacer and a top spacer; 
 a top source-drain region formed on the top spacer; and 
 a metal contact formed on the top source-drain region; and 
 
 a long channel device in the substrate, wherein the long channel device is a second vertical FET comprising:
 a plurality of fins, wherein sets of adjacent fins from the plurality of fins have connected bottom source-drain regions; 
 a plurality of gates formed between a second top spacer and a second bottom spacer, wherein the plurality of gates are physically separated; 
 top source-drain regions formed on the second top spacer for each fin of the plurality of fins; and 
 a plurality of metal contacts connecting, for each of the sets, the top source-drain regions of the adjacent fins. 
 
 
     
     
       18. The semiconductor device according to  claim 17 , wherein:
 the plurality of gates are physically separated by a dielectric material on the substrate, wherein the substrate comprises a silicon substrate for both the long channel device and the short channel device. 
 
     
     
       19. The semiconductor device of  claim 17 , further comprising wells formed and defining the bottom source region of the short channel device and the connected bottom source-drain regions of the long channel device. 
     
     
       20. The semiconductor device of  claim 17 , wherein the gate of the short channel device and the plurality of gates of the long channel device have a same gate length.