Memory sub-system with dynamic calibration using component-based function(s)

Abstract

An apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.

We claim: 
     
       1. An apparatus comprising:
 a circuit configured to generate, in response to a data access command from a controller, two or more read results based on reading data using a read level voltage and at least one offset read voltage, wherein—
 the two or more read results are generated in calibrating the read level voltage initially configured for use in response to a read command, and 
 the data access command is different from the read command. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein:
 the circuit configured to generate the two or more read results is a first circuit; 
 further comprising: 
 a second circuit coupled to the first circuit and configured to receive the data access command from the controller. 
 
     
     
       3. The apparatus of  claim 1 , wherein the data is read from memory cells comprising a non-volatile memory device. 
     
     
       4. The apparatus of  claim 1 , wherein the circuitry is further configured to:
 identify a targeted read setting designated by the controller for a set of memory cells; and 
 identify a read set that corresponds to the test read setting, wherein the read set includes the two or more read results for the data stored at the set of memory cells. 
 
     
     
       5. The apparatus of  claim 1 , wherein the identified target read setting includes:
 a plurality of bits that each correspond to a read level specific to a page type, and 
 a control mask set masking one or more bits in the target read setting separate from the test target. 
 
     
     
       6. The apparatus of  claim 1 , wherein the data access command is a single command that is configured to operate the circuit to perform multiple read operations on a corresponding set of memory cells with different read voltages. 
     
     
       7. The apparatus of  claim 6 , wherein the circuit is configured to respond to the data access command by outputting to the controller one result from the multiple read operations. 
     
     
       8. The apparatus of  claim 7 , wherein the circuit is configured to provide, in response to an additional command, one or more remaining results from a remainder of the multiple read operations. 
     
     
       9. The apparatus of  claim 6 , wherein the circuit includes an internal storage circuit configured to store the two or more read results and/or corresponding read voltages. 
     
     
       10. The apparatus of  claim 1 , wherein the circuit is configured to implement a dummy read for initially reading from a set of memory cells before generating the two or more read results, wherein the dummy read is for eliminating transient reactions without providing access to read data. 
     
     
       11. A method comprising:
 receiving a data access command from a controller; and 
 in response to one or each received data access command, generating two or more read results based on reading data using a read level voltage and at least one offset read voltage, wherein—
 the two or more read results are generated in calibrating the read level voltage initially configured for use in response to a read command, and 
 the data access command is different from the read command. 
 
 
     
     
       12. The method of  claim 11 , further comprising:
 storing the two or more read results; and 
 providing one of the two or more read results to the controller as a response to the data access command. 
 
     
     
       13. The method of  claim 12 , further comprising:
 receiving a second command after the data access command; and 
 providing a second of the two or more read results as a response to the second command. 
 
     
     
       14. The method of  claim 11 , further comprising:
 accessing a control register to identify a targeted read setting for a set of memory cells having the data stored therein; and 
 identifying a read set that includes the two or more read results generated by reading from the set of memory cells using the read level voltage and the at least one offset read voltage. 
 
     
     
       15. The method of  claim 11 , further comprising performing a dummy before generating the two or more read results. 
     
     
       16. The method of  claim 11 , further comprising:
 based on the two or more read results, determining error rates for each of the read level voltage and the at least one offset read voltage; and 
 dynamically calibrating the read level voltage to one of the voltages having a lowest error rate within the set of error rates. 
 
     
     
       17. The method of  claim 16 , wherein:
 the at least one offset read voltage includes (1) a positively offset voltage greater than the read level voltage and (2) a negatively offset voltage less than the read level voltage, wherein the positively and negatively offset voltages correspond to a shared offset magnitude; 
 the set of error rates includes (1) a positive offset rate corresponding to the positively offset voltage, (2) a negative offset rate corresponding to the negatively offset voltage, and (3) a center rate corresponding to the read level voltage; and 
 dynamically calibrating the read level voltage includes increasing or decreasing the read level voltage toward or to the positive or the negative offset rate having the lowest error rate. 
 
     
     
       18. A system comprising circuitry configured to:
 generate, in response to a data access command, two or more read results using a read level voltage and at least one offset read voltage; 
 determine an error rate for each of the read level voltage and the at least one offset read voltage based on the two or more read results; and 
 setting the read level voltage to equal the at least one offset read voltage when the corresponding error rate is lower than that of the read level voltage. 
 
     
     
       19. The system of  claim 18 , wherein the circuitry comprises a memory controller. 
     
     
       20. The system of  claim 18 , further comprising:
 a memory device coupled to the circuitry, 
 wherein the data access command is different from a read command configured to generate a read result based on reading the set of memory cells using the read level voltage.