Circuit board structure and manufacturing method thereof

Abstract

A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

What is claimed is: 
     
       1. A circuit board structure, comprising:
 a carrier; 
 a thin film redistribution layer disposed on the carrier, wherein the thin film redistribution layer comprises a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer, the first dielectric layer has a first surface and a second surface opposite to each other and a plurality of first openings extending from the second surface towards the first surface, the first openings expose part of the pads, the first surface is higher than an upper surface of each of the pads, the first metal layer is disposed on the second surface of the first dielectric layer and extends into the first openings, the second dielectric layer covers the first dielectric layer and the first metal layer and has a plurality of second openings exposing part of the first metal layer, the second metal layer is disposed on the second dielectric layer, extends into the second openings, and is electrically connected to the first metal layer, and the third dielectric layer covers the second dielectric layer and the second metal layer and has a plurality of third openings exposing part of the second metal layer; 
 a plurality of solder balls disposed in the third openings of the third dielectric layer of the thin film redistribution layer, wherein the solder balls are electrically connected to second metal layer of the thin film redistribution layer and the carrier; and 
 a surface treatment layer disposed on the upper surface of each of the pads, wherein a top surface of the surface treatment layer is higher than the first surface of the first dielectric layer, wherein the surface treatment layer comprises a first surface treatment layer and a second surface treatment layer, and a first thickness of the first surface treatment layer is greater than a second thickness of the second surface treatment layer. 
 
     
     
       2. The circuit board structure according to  claim 1 , wherein the first dielectric layer further comprises a plurality of fourth openings extending from the first surface towards the second surface, the fourth openings at least expose the upper surfaces of the pads, the first surface treatment layer is disposed in each of the fourth openings and protrudes from the first surface of the first dielectric layer, and the second surface treatment layer covers the first surface treatment layer. 
     
     
       3. The circuit board structure according to  claim 1 , wherein the first dielectric layer further comprises a plurality of fourth openings extending from the first surface towards the second surface, the fourth openings expose part of the first metal layer and are defined as the pads, the first surface treatment layer is disposed in each of the fourth openings, and the second surface treatment layer is disposed on the first surface treatment layer and protrudes from the first surface of the first dielectric layer. 
     
     
       4. The circuit board structure according to  claim 1 , further comprising:
 a patterned seed layer disposed on the first metal layer, wherein the first dielectric layer further comprises a plurality of fourth openings extending from the first surface towards the second surface, the fourth openings expose part of the patterned seed layer and are defined as the pads, the first surface treatment layer is disposed in each of the fourth openings and is aligned with the first surface of the first dielectric layer, and the second surface treatment layer is disposed on the first surface treatment layer. 
 
     
     
       5. The circuit board structure according to  claim 1 , further comprising:
 an underfill filled between the third dielectric layer of the thin film redistribution layer and the carrier and covering the solder balls. 
 
     
     
       6. The circuit board structure according to  claim 5 , wherein a peripheral surface of the thin film redistribution layer is aligned with a peripheral surface of the underfill and a peripheral surface of the carrier. 
     
     
       7. A manufacturing method of a circuit board structure, comprising:
 forming a thin film redistribution layer on a temporary carrier, wherein the thin film redistribution layer comprises a metal layer, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer, the metal layer and the first dielectric layer are formed on the temporary carrier, the first dielectric layer has a plurality of first openings exposing part of the metal layer, the first metal layer is formed on the first dielectric layer, extends into the first openings, and is electrically connected to the metal layer, the second dielectric layer covers the first dielectric layer and the first metal layer and has a plurality of second openings exposing part of the first metal layer, the second metal layer is disposed on the second dielectric layer, extends into the second openings, and is electrically connected to the first metal layer, and the third dielectric layer covers the second dielectric layer and the second metal layer and has a plurality of third openings exposing part of the second metal layer; 
 assembling the thin film redistribution layer onto a carrier through a plurality of solder balls, wherein the solder balls are located in the third openings of the third dielectric layer, and the solder balls are electrically connected to the second metal layer and the carrier; 
 removing the temporary carrier to expose a first surface of the first dielectric layer and the metal layer and removing at least part of the metal layer to form a plurality of pads after assembling the thin film redistribution layer onto the carrier, wherein the first surface of the first dielectric layer is higher than an upper surface of each of the pads; and 
 forming a surface treatment layer on the upper surface of each of the pads, wherein a top surface of the surface treatment layer is higher than the first surface of the first dielectric layer. 
 
     
     
       8. The manufacturing method of the circuit board structure according to  claim 7 , wherein the temporary carrier comprises a glass substrate, a release film, and a seed layer, the release film is located between the glass substrate and the seed layer, and the step of forming the thin film redistribution layer on the temporary carrier comprises:
 forming the metal layer on the seed layer; 
 forming the first dielectric layer on the release film, wherein the first dielectric layer covers the metal layer, and the first openings expose part of the metal layer; 
 forming a first patterned seed layer and the first metal layer thereon on the first dielectric layer and the metal layer; 
 forming the second dielectric layer on the first dielectric layer; 
 forming a second patterned seed layer and the second metal layer thereon on the second dielectric layer and in the second openings; and 
 forming the third dielectric layer on the second dielectric layer. 
 
     
     
       9. The manufacturing method of the circuit board structure according to  claim 8 , further comprising:
 forming an electroplating seed layer on a side of the carrier relatively away from the thin film redistribution layer after removing the temporary carrier and before removing at least part of the metal layer to form the pads; and 
 forming a plating resist layer on the electroplating seed layer and exposing part of the electroplating seed layer to form a plurality of electroplating contact points. 
 
     
     
       10. The manufacturing method of the circuit board structure according to  claim 9 , wherein the step of forming the surface treatment layer comprises:
 performing an electroplating process with the electroplating contact points to form the surface treatment layer on the upper surface of each of the pads, wherein the surface treatment layer comprises a first surface treatment layer and a second surface treatment layer, and a first thickness of the first surface treatment layer is greater than a second thickness of the second surface treatment layer. 
 
     
     
       11. The manufacturing method of the circuit board structure according to  claim 10 , wherein the step of removing at least part of the metal layer comprises:
 removing the seed layer and part of the metal layer by etching to form the pads, wherein the first dielectric layer forms a plurality of fourth openings extending from the first surface towards the second surface, the fourth openings at least expose the upper surface of each of the pads, the first surface treatment layer is formed in each of the fourth openings and protrudes from the first surface of the first dielectric layer, and the second surface treatment layer covers the first surface treatment layer. 
 
     
     
       12. The manufacturing method of the circuit board structure according to  claim 10 , wherein the step of removing at least part of the metal layer comprises:
 completely removing the seed layer, the metal layer, and part of the first patterned seed layer by etching and exposing part of the first metal layer to be defined as the pads, wherein the first dielectric layer forms a plurality of fourth openings extending from the first surface towards the second surface, the fourth openings at least expose the upper surface of each of the pads, the first surface treatment layer is formed in each of the fourth openings, and the second surface treatment layer is formed on the first surface treatment layer and protrudes from the first surface of the first dielectric layer. 
 
     
     
       13. The manufacturing method of the circuit board structure according to  claim 10 , wherein the step of removing at least part of the metal layer comprises:
 completely removing the seed layer and the metal layer by etching and exposing part of the first patterned seed layer to be defined as the pads, wherein the first dielectric layer forms a plurality of fourth openings extending from the first surface towards the second surface, the fourth openings at least expose the upper surface of each of the pads, the first surface treatment layer is formed in each of the fourth openings and is aligned with the first surface of the first dielectric layer, and the second surface treatment layer is formed on the first surface treatment layer. 
 
     
     
       14. The manufacturing method of the circuit board structure according to  claim 7 , further comprising:
 filling an underfill between the third dielectric layer of the thin film redistribution layer and the carrier and covering the solder balls before removing the temporary carrier. 
 
     
     
       15. The manufacturing method of the circuit board structure according to  claim 14 , further comprising:
 performing a singulation process to cut the thin film redistribution layer, the underfill, and the carrier after the step of forming the surface treatment layer, so that a peripheral surface of the thin film redistribution layer is aligned with a peripheral surface of the underfill and a peripheral surface of the carrier. 
 
     
     
       16. A circuit board structure, comprising:
 a thin film redistribution layer comprising a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer, the first dielectric layer has a first surface and a second surface opposite to each other and a plurality of first openings extending from the second surface towards the first surface, the first openings expose part of the pads, the first surface is higher than an upper surface of each of the pads, the first metal layer is disposed on the second surface of the first dielectric layer and extends into the first openings, the second dielectric layer covers the first dielectric layer and the first metal layer and has a plurality of second openings exposing part of the first metal layer, the second metal layer is disposed on the second dielectric layer, extends into the second openings, and is electrically connected to the first metal layer, and the third dielectric layer covers the second dielectric layer and the second metal layer and has a plurality of third openings exposing part of the second metal layer; and 
 a surface treatment layer disposed on the upper surface of each of the pads, wherein a top surface of the surface treatment layer is higher than the first surface of the first dielectric layer, wherein the surface treatment layer comprises a first surface treatment layer and a second surface treatment layer, and a first thickness of the first surface treatment layer is greater than a second thickness of the second surface treatment layer.