Redistribution layer having a sideview zig-zag profile

Abstract

A semiconductor device package includes a semiconductor device and an electrically conductive pad disposed in contact with a surface of the semiconductor device. The semiconductor device package further includes a redistribution layer (RDL) formed over the electrically conductive pad and the surface of the semiconductor device, and an electrical connector disposed over and electrically coupled to the RDL. The RDL includes a first passivation layer disposed over a surface of the semiconductor device and the electrically conductive pad, and further includes an RDL trace. The RDL trace includes a first portion in contact with the electrically conductive pad, a second portion in contact with one of the electrical connector or an underlying metallization layer in contact with the electrical connector, and a third portion having a non-planar and undulating configuration relative to the surface of the semiconductor device.

What is claimed is: 
     
       1. A semiconductor device package comprising:
 a semiconductor chip; 
 a first re-passivation layer disposed over a surface of the semiconductor device chip, wherein the first re-passivation layer includes an opening that exposes a top surface of an electrically conductive pad, and the first re-passivation layer further includes a non-planar portion relative to the surface of the semiconductor chip adjacent to the opening; and 
 a redistribution layer (RDL) trace disposed in conformal contact with the first re-passivation layer, wherein the RDL trace comprises a non-planar configuration relative to the surface of the semiconductor chip adjacent to the opening, wherein the non-planar configuration comprises a first area of the RDL trace having a first height and a second area of the RDL trace having a second height different than the first height. 
 
     
     
       2. The semiconductor device package of  claim 1 , wherein the non-planar configuration comprises at least one peak and at least one valley in the RDL trace. 
     
     
       3. The semiconductor device package of  claim 1 , wherein the semiconductor device package further comprises:
 the electrically conductive pad disposed below the first passivation layer and in contact with the semiconductor chip and the RDL trace; 
 a second re-passivation layer disposed above and in contact with the RDL trace; and 
 an electrical connector disposed above and electrically coupled to the RDL trace. 
 
     
     
       4. The semiconductor device package of  claim 3 , further comprising:
 a metallization layer disposed between the RDL trace and the electrical connector, wherein a first surface of the metallization layer contacts the RDL trace, and a second surface of the metallization layer contacts the electrical connector. 
 
     
     
       5. The semiconductor device package of  claim 3 , further comprising:
 a passivation layer in contact with the surface of the semiconductor device and a bottom surface of the first re-passivation layer, and further in contact with the electrically conductive pad. 
 
     
     
       6. The semiconductor device package of  claim 3 , wherein the RDL trace comprises a first portion in contact with the electrically conductive pad, a second portion in contact with the electrical connector, and a third portion comprising the non-planar configuration, wherein the third portion is disposed between the first portion and the second portion of the RDL trace. 
     
     
       7. The semiconductor device package of  claim 6 , wherein a first surface of the third portion of the RDL trace transitioning from the first area of the RDL trace having the first height to the second area of the RDL trace having the second height is sloped such that a first obtuse angle is formed between the first area and the second area, and wherein a second surface of the third portion of the RDL trace transitioning from the second area to a third area of the RDL trace having a third height is sloped such that a second obtuse angle is formed between the second area and third area. 
     
     
       8. The semiconductor device package of  claim 1 , wherein the non-planar portion of the first re-passivation layer includes at least one peak having a first height above a bottom surface of the first re-passivation layer and at least one valley having a second height above the bottom surface of the first re-passivation layer, wherein the first height is greater than the second height. 
     
     
       9. The semiconductor device package of  claim 8 , wherein a range of a height difference between the first height of the at least one peak and the second height of the at least one valley is at least 2 micrometers. 
     
     
       10. The semiconductor device package of  claim 8 , wherein a range of a height difference between the first height of the at least one peak and the second height of the at least one valley is at least 5 micrometers. 
     
     
       11. The semiconductor device package of  claim 8 , wherein a thickness of the first re-passivation layer at the at least one valley is at least 5 micrometers. 
     
     
       12. The semiconductor device package of  claim 8 , wherein the non-planar portion of the first re-passivation layer includes multiple peaks having the first height above the bottom surface of the first re-passivation layer and multiple valleys having the second height above the bottom surface of the first re-passivation layer. 
     
     
       13. The semiconductor device package of  claim 8 , wherein the non-planar configuration of the RDL trace has a pattern along a plane orthogonal to the surface of the semiconductor chip that is selected from a group consisting of a hilling topography, a zig-zag pattern, a folding pattern, an undulating pattern, and a quasi-sinusoidal pattern. 
     
     
       14. A semiconductor device package comprising:
 a semiconductor chip; 
 an electrically conductive pad disposed in contact with the semiconductor chip; 
 a redistribution layer (RDL) formed over the electrically conductive pad; and 
 an electrical connector disposed over and electrically coupled to the RDL, wherein the RDL comprises: 
 a first re-passivation layer disposed over a surface of the semiconductor chip, wherein the first re-passivation layer includes an opening that exposes a top surface of the electrically conductive pad, and the first re-passivation layer further includes a non-planar portion relative to the surface of the semiconductor chip between the opening and the electrical connector; and 
 an RDL trace comprising a first portion in contact with the electrically conductive pad, a second portion in contact with one of the electrical connector or an underlying metallization layer in contact with the electrical connector, and a third portion in conformal contact with the first re-passivation layer so that the RDL trace has a non-planar configuration relative to the surface of the semiconductor chip between the opening and the electrical connector. 
 
     
     
       15. The semiconductor device package of  claim 14 , wherein the non-planar configuration comprises at least one peak and at least one valley in the RDL trace. 
     
     
       16. The semiconductor device package of  claim 15 , wherein the at least one peak is disposed in at least a first area of the third portion of the RDL trace having a first height and the at least one valley is disposed in at least a second area of the third portion of the RDL trace having a second height different than the first height, and wherein a surface of the RDL trace transitioning from the first area to the second area is sloped such that an obtuse angle is formed between the first area and the second area. 
     
     
       17. A method of fabricating a semiconductor device package, comprising:
 forming a first re-passivation layer over a surface of an underlying semiconductor chip device; 
 patterning the first re-passivation layer, wherein the patterning forms an opening that exposes a top surface of an electrically conductive pad and a first non-planar and undulating configuration in a portion of the first re-passivation layer relative to the surface of the semiconductor chip adjacent to the opening; and 
 forming a redistribution layer (RDL) trace in contact with the patterned first re-passivation layer, wherein the RDL trace comprises a second non-planar and undulating configuration relative to the surface of the semiconductor chip adjacent to the opening and conforming to the first non-planar and undulating configuration. 
 
     
     
       18. The method of  claim 17 , wherein the first non-planar and undulating configuration and the second non-planar and undulating configuration each comprise at least one peak and at least one valley. 
     
     
       19. The method of  claim 17 , wherein the first re-passivation layer is patterned using at least one of a grayscale mask or a multi-exposure process. 
     
     
       20. The method of  claim 17 , wherein patterning the first re-passivation layer forms the opening in the first re-passivation layer that exposes the electrically conductive pad, and wherein the electrically conductive pad is in contact with the semiconductor chip.